;*****************************************************************
;* This stationery serves as the framework for a                 *
;* user application (single file, absolute assembly application) *
;* For a more comprehensive program that                         *
;* demonstrates the more advanced functionality of this          *
;* processor, please see the demonstration applications          *
;* located in the examples subdirectory of the                   *
;* Freescale CodeWarrior for the HC12 Program directory          *
;*****************************************************************

; export symbols
            XDEF Entry, _Startup            ; export 'Entry' symbol
            ABSENTRY Entry        ; for absolute assembly: mark this as application entry point



; Include derivative-specific definitions 
		INCLUDE 'derivative.inc' 

ROMStart    EQU  $4000  ; absolute address to place my code/constant data

; variable/data section

            ORG RAMStart
 ; Insert here your data definition.

; code section
            ORG   ROMStart


Entry:
_Startup:
      ;**********OPCIONAL*************************
      ldaa #$18      ;configuracion del PLL
      staa SYNR      ;SYNR=24
      ldaa #$07      
      staa REFDV     ;REFDV=7
      ldaa #$80
      staa CLKSEL    ;se selecciona la opcion de PLL
      ldaa #$60
      staa PLLCTL    ;se enciende la opcion de PLL
      ;********************************************





      ;CONFIGURACION DEL PWM
      
      movb #$02, PWMPRCLK  ;clockA=25Mhz/4
      movb #$C2, PWMSCLA   ;clockSA=CLockA/(2*194)
      movb #$01, PWMCLK    ;ClockSA habilitado para pwm canal 0
      clr PWMPOL           ;Inicia el pulso a nivel bajo
      clr PWMCAE           ;Alineacion a la izquierda
      clr PWMCTL           ;
      
      ;programa principal
      loop:
      ldaa #$FF      
      staa PWMPER0         ;PWM_FREC = CLockSA/PWMPER0  carga el valor que tiene el periodo PWM_FREC=63Hz
      movb #$01,PWME 
      loop1:
      staa PWMDTY0         ;PWMDTY0 contiene el ciclo de trabajo
      deca
      jsr retardo
      bne loop1 
      bra loop
      




retardo:
      ldx #$FF
ret2:
      ldy #$FF            ;//ldy #$ffff
ret:  
      nop
      DBNE y,ret
      DBNE x,ret2
      RTS
       
        

;**************************************************************
;*                 Interrupt Vectors                          *
;**************************************************************
            ORG   $FFFE
            DC.W  Entry           ; Reset Vector