cont_modN Project Status
Project File: cont_modN.xise Parser Errors: No Errors
Module Name: cont_modN Implementation State: Synthesized
Target Device: xc3s100e-5cp132
  • Errors:
 No Errors
Product Version:ISE 12.2
  • Warnings:
 No Warnings
Design Goal: Balanced
  • Routing Results:
  
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
  
Environment: System Settings
  • Final Timing Score:
   
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slices 5 960 0%
Number of Slice Flip Flops 6 1920 0%
Number of 4 input LUTs 9 1920 0%
Number of bonded IOBs 8 83 9%
Number of GCLKs 1 24 4%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentjue 28. oct 10:22:44 2010000
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 10/31/2010 - 15:14:29