;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** ;***** Created: 2007-12-13 07:27 ******* Source: ATmega8515.xml ********** ;************************************************************************* ;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y ; * ; * Número: AVR000 ; * Nombre del archivo: "m8515def.inc" ; * Título: Registrarse / Definiciones de bits para los ATMEGA8515 ; * Fecha: 2007-12-13 ; * Versión: 2.24 ; * Apoyo E-mail: avr@atmel.com ; * MCU Objetivo: ATMEGA8515 ; * ; * DESCRIPCIÓN ; * Al incluir este archivo en el archivo de programa de la asamblea, todo registro de E / S ; * Los nombres y los nombres de E / S de registro de bits que aparecen en el libro de datos pueden ser utilizados. ; * Además, los seis registros que forman los tres punteros de datos X, Y y ; * Z se han asignado nombres XL - ZH. Mejor dirección de RAM interna ; * SRAM también se define ; * ; * Los nombres de Registro están representados por su dirección hexadecimal. ; * ; * Los nombres de registro de bits están representados por su número de bits (0-7). ; * ; * Tenga en cuenta la diferencia en el uso de los nombres de bits con instrucciones ; * Como "sbr" / "cbr" (set / poco claro en el registro) y "SBR" / "SBRC" ; * (Saltar si el bit en el registro del sistema / de borra). El siguiente ejemplo ilustra ; * Esto: ; * ; * En r16, PORTB; leer PORTB pestillo ; * Sbr r16, (1 << PB6) + (1 << PB5); establecer PB6 y PB5 (uso de máscaras, no bit #) ; * Salida PORTB, r16, y la salida a PORTB ; * ; * En r16, TIFR; leer la bandera de interrupción Registro Timer ; * R16 SBRC, TOV0; prueba el indicador de desbordamiento (uso poco #) ; * Rjmp TOV0_is_set; salto si se ha ajustado ; * ..., De lo contrario hacer otra cosa ; ************************************************* ************************ #ifndef _M8515DEF_INC_ #define _M8515DEF_INC_ #pragma partinc 0 ; ***** SPECIFY DEVICE *************************************************** .device ATmega8515 #pragma AVRPART ADMIN PART_NAME ATmega8515 .equ SIGNATURE_000 = 0x1e .equ SIGNATURE_001 = 0x93 .equ SIGNATURE_002 = 0x06 #pragma AVRPART CORE CORE_VERSION V2E ; ***** I/O REGISTER DEFINITIONS ***************************************** ; NOTE: ; Definitions marked "MEMORY MAPPED"are extended I/O ports ; and cannot be used with IN/OUT instructions .equ SREG = 0x3f .equ SPL = 0x3d .equ SPH = 0x3e .equ GICR = 0x3b .equ GIFR = 0x3a .equ TIMSK = 0x39 .equ TIFR = 0x38 .equ SPMCR = 0x37 .equ EMCUCR = 0x36 .equ MCUCR = 0x35 .equ MCUCSR = 0x34 .equ TCCR0 = 0x33 .equ TCNT0 = 0x32 .equ OCR0 = 0x31 .equ SFIOR = 0x30 .equ TCCR1A = 0x2f .equ TCCR1B = 0x2e .equ TCNT1L = 0x2c .equ TCNT1H = 0x2d .equ OCR1AL = 0x2a .equ OCR1AH = 0x2b .equ OCR1BL = 0x28 .equ OCR1BH = 0x29 .equ ICR1L = 0x24 .equ ICR1H = 0x25 .equ WDTCR = 0x21 .equ UBRRH = 0x20 .equ UCSRC = 0x20 .equ EEARL = 0x1e .equ EEARH = 0x1f .equ EEDR = 0x1d .equ EECR = 0x1c .equ PORTA = 0x1b .equ DDRA = 0x1a .equ PINA = 0x19 .equ PORTB = 0x18 .equ DDRB = 0x17 .equ PINB = 0x16 .equ PORTC = 0x15 .equ DDRC = 0x14 .equ PINC = 0x13 .equ PORTD = 0x12 .equ DDRD = 0x11 .equ PIND = 0x10 .equ SPDR = 0x0f .equ SPSR = 0x0e .equ SPCR = 0x0d .equ UDR = 0x0c .equ UCSRA = 0x0b .equ UCSRB = 0x0a .equ UBRRL = 0x09 .equ ACSR = 0x08 .equ PORTE = 0x07 .equ DDRE = 0x06 .equ PINE = 0x05 .equ OSCCAL = 0x04 ; ***** BIT DEFINITIONS ************************************************** ; ***** ANALOG_COMPARATOR ************ ; ACSR - Analog Comparator Control And Status Register .equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 .equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 .equ ACIC = 2 ; Analog Comparator Input Capture Enable .equ ACIE = 3 ; Analog Comparator Interrupt Enable .equ ACI = 4 ; Analog Comparator Interrupt Flag .equ ACO = 5 ; Analog Compare Output .equ ACBG = 6 ; Analog Comparator Bandgap Select .equ AINBG = ACBG ; For compatibility .equ ACD = 7 ;Analog Comparator Disable ; ***** USART ************************ ; UDR - USART I/O Data Register .equ UDR0 = 0 ; USART I/O Data Register bit 0 .equ UDR1 = 1 ; USART I/O Data Register bit 1 .equ UDR2 = 2 ; USART I/O Data Register bit 2 .equ UDR3 = 3 ; USART I/O Data Register bit 3 .equ UDR4 = 4 ; USART I/O Data Register bit 4 .equ UDR5 = 5 ; USART I/O Data Register bit 5 .equ UDR6 = 6 ; USART I/O Data Register bit 6 .equ UDR7 = 7 ; USART I/O Data Register bit 7 ; UCSRA - USART Control and Status Register A .equ MPCM = 0 ; Multi-processor Communication Mode .equ U2X = 1 ; Double the USART transmission speed .equ UPE = 2 ; Parity Error .equ PE = UPE ; For compatibility .equ DOR = 3 ; Data overRun .equ FE = 4 ; Framing Error .equ UDRE = 5 ; USART Data Register Empty .equ TXC = 6 ; USART Transmitt Complete .equ RXC = 7 ; USART Receive Complete ; UCSRB - USART Control and Status Register B .equ TXB8 = 0 ; Transmit Data Bit 8 .equ RXB8 = 1 ; Receive Data Bit 8 .equ UCSZ2 = 2 ; Character Size Bit 2 .equ CHR9 = UCSZ2 ; For compatibility .equ TXEN = 3 ; Transmitter Enable .equ RXEN = 4 ; Receiver Enable .equ UDRIE = 5 ; USART Data register Empty Interrupt Enable .equ TXCIE = 6 ; TX Complete Interrupt Enable .equ RXCIE = 7 ; RX Complete Interrupt Enable ; UCSRC - USART Control and Status Register C .equ UCPOL = 0 ; Clock Polarity .equ UCSZ0 = 1 ; Character Size Bit 0 .equ UCSZ1 = 2 ; Character Size Bit 1 .equ USBS = 3 ; Stop Bit Select .equ UPM0 = 4 ; Parity Mode Bit 0 .equ UPM1 = 5 ; Parity Mode Bit 1 .equ UMSEL = 6 ; USART Mode Select .equ URSEL = 7 ; Register Select ; UBRRH - USART Baud Rate Register High Byte .equ UBRR8 = 0 ; USART Baud Rate Register bit 8 .equ UBRR9 = 1 ; USART Baud Rate Register bit 9 .equ UBRR10 = 2 ; USART Baud Rate Register bit 10 .equ UBRR11 = 3 ; USART Baud Rate Register bit 11 ;.equ URSEL = 7 ; Register Select ; ***** SPI ************************** ; SPDR - SPI Data Register .equ SPDR0 = 0 ; SPI Data Register bit 0 .equ SPDR1 = 1 ; SPI Data Register bit 1 .equ SPDR2 = 2 ; SPI Data Register bit 2 .equ SPDR3 = 3 ; SPI Data Register bit 3 .equ SPDR4 = 4 ; SPI Data Register bit 4 .equ SPDR5 = 5 ; SPI Data Register bit 5 .equ SPDR6 = 6 ; SPI Data Register bit 6 .equ SPDR7 = 7 ; SPI Data Register bit 7 ; SPSR - SPI Status Register .equ SPI2X = 0 ; Double SPI Speed Bit .equ WCOL = 6 ; Write Collision Flag .equ SPIF = 7 ; SPI Interrupt Flag ; SPCR - SPI Control Register .equ SPR0 = 0 ; SPI Clock Rate Select 0 .equ SPR1 = 1 ; SPI Clock Rate Select 1 .equ CPHA = 2 ; Clock Phase .equ CPOL = 3 ; Clock polarity .equ MSTR = 4 ; Master/Slave Select .equ DORD = 5 ; Data Order .equ SPE = 6 ; SPI Enable .equ SPIE = 7 ; SPI Interrupt Enable ; ***** CPU ************************** ; SREG - Status Register .equ SREG_C = 0 ; Carry Flag .equ SREG_Z = 1 ; Zero Flag .equ SREG_N = 2 ; Negative Flag .equ SREG_V = 3 ; Two's Complement Overflow Flag .equ SREG_S = 4 ; Sign Bit .equ SREG_H = 5 ; Half Carry Flag .equ SREG_T = 6 ; Bit Copy Storage .equ SREG_I = 7 ; Global Interrupt Enable ; EMCUCR - Extended MCU Control Register .equ ISC2 = 0 ; Interrupt Sense Control 2 .equ SRW11 = 1 ; Wait State Select Bits for Upper Sector, bit 1 .equ SRW00 = 2 ; Wait State Select Bits for Lower Sector, bit 0 .equ SRW01 = 3 ; Wait State Select Bits for Lower Sector, bit 1 .equ SRL0 = 4 ; Wait State Selector Limit bit 0 .equ SRL1 = 5 ; Wait State Selector Limit bit 1 .equ SRL2 = 6 ; Wait State Selector Limit bit 2 .equ SM0 = 7 ; Sleep Mode Select Bit 0 ; MCUCR - MCU Control Register .equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0 .equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1 .equ ISC10 = 2 ; Interrupt Sense Control 1 Bit 0 .equ ISC11 = 3 ; Interrupt Sense Control 1 Bit 1 .equ SM1 = 4 ; Sleep Mode Select Bit 1 .equ SE = 5 ; Sleep Enable .equ SRW10 = 6 ; Wait State Select Bits for Upper Sector, bit 0 .equ SRE = 7 ; External SRAM/XMEM Enable ; MCUCSR - MCU Control And Status Register .equ MCUSR = MCUCSR ; For compatibility .equ PORF = 0 ; Power-on reset flag .equ EXTRF = 1 ; External Reset Flag .equ BORF = 2 ; Brown-out Reset Flag .equ WDRF = 3 ; Watchdog Reset Flag .equ SM2 = 5 ; Sleep Mode Select Bit 2 ; OSCCAL - Oscillator Calibration Value .equ CAL0 = 0 ; Oscillator Calibration Value Bit0 .equ CAL1 = 1 ; Oscillator Calibration Value Bit1 .equ CAL2 = 2 ; Oscillator Calibration Value Bit2 .equ CAL3 = 3 ; Oscillator Calibration Value Bit3 .equ CAL4 = 4 ; Oscillator Calibration Value Bit4 .equ CAL5 = 5 ; Oscillator Calibration Value Bit5 .equ CAL6 = 6 ; Oscillator Calibration Value Bit6 .equ CAL7 = 7 ; Oscillator Calibration Value Bit7 ; SPMCR - Store Program Memory Control Register .equ SPMEN = 0 ; Store Program Memory Enable .equ PGERS = 1 ; Page Erase .equ PGWRT = 2 ; Page Write .equ BLBSET = 3 ; Boot Lock Bit Set .equ RWWSRE = 4 ; Read-While-Write Section Read Enable .equ ASRE = RWWSRE ; For compatibility .equ RWWSB = 6 ; Read-While-Write Section Busy .equ ASB = RWWSB ; For compatibility .equ SPMIE = 7 ; SPM Interrupt Enable ; SFIOR - Special Function IO Register .equ PSR10 = 0 ; Prescaler Reset Timer / Counter 1 and Timer / Counter 0 .equ PUD = 2 ; Pull-up Disable .equ XMM0 = 3 ; External Memory High Mask Bit 0 .equ XMM1 = 4 ; External Memory High Mask Bit 1 .equ XMM2 = 5 ; External Memory High Mask Bit 2 .equ XMBK = 6 ; External Memory Bus Keeper Enable ; ***** EXTERNAL_INTERRUPT *********** ; GICR - General Interrupt Control Register .equ GIMSK = GICR ; For compatibility .equ IVCE = 0 ; Interrupt Vector Change Enable .equ IVSEL = 1 ; Interrupt Vector Select .equ INT2 = 5 ; External Interrupt Request 2 Enable .equ INT0 = 6 ; External Interrupt Request 0 Enable .equ INT1 = 7 ; External Interrupt Request 1 Enable ; GIFR - General Interrupt Flag Register .equ INTF2 = 5 ; External Interrupt Flag 2 .equ INTF0 = 6 ; External Interrupt Flag 0 .equ INTF1 = 7 ; External Interrupt Flag 1 ; ***** WATCHDOG ********************* ; WDTCR - Watchdog Timer Control Register .equ WDTCSR = WDTCR ; For compatibility .equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 .equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 .equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 .equ WDE = 3 ; Watch Dog Enable .equ WDCE = 4 ; Watchdog Change Enable .equ WDTOE = WDCE ; For compatibility ; ***** TIMER_COUNTER_0 ************** ; TCCR0 - Timer/Counter 0 Control Register .equ CS00 = 0 ; Clock Select 0 .equ CS01 = 1 ; Clock Select 1 .equ CS02 = 2 ; Clock Select 2 .equ WGM01 = 3 ; Waveform Generation Mode 1 .equ CTC0 = WGM01 ; For compatibility .equ COM00 = 4 ; Compare match Output Mode 0 .equ COM01 = 5 ; Compare Match Output Mode 1 .equ WGM00 = 6 ; Waveform Generation Mode 0 .equ PWM0 = WGM00 ; For compatibility .equ FOC0 = 7 ; Force Output Compare ; TCNT0 - Timer/Counter 0 Register .equ TCNT0_0 = 0 ; .equ TCNT0_1 = 1 ; .equ TCNT0_2 = 2 ; .equ TCNT0_3 = 3 ; .equ TCNT0_4 = 4 ; .equ TCNT0_5 = 5 ; .equ TCNT0_6 = 6 ; .equ TCNT0_7 = 7 ; ; OCR0 - Timer/Counter 0 Output Compare Register .equ OCR0_0 = 0 ; .equ OCR0_1 = 1 ; .equ OCR0_2 = 2 ; .equ OCR0_3 = 3 ; .equ OCR0_4 = 4 ; .equ OCR0_5 = 5 ; .equ OCR0_6 = 6 ; .equ OCR0_7 = 7 ; ; TIMSK - Timer/Counter Interrupt Mask Register .equ OCIE0 = 0 ; Timer/Counter0 Output Compare Match Interrupt register .equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable ; TIFR - Timer/Counter Interrupt Flag register .equ OCF0 = 0 ; Output Compare Flag 0 .equ TOV0 = 1 ; Timer/Counter0 Overflow Flag ; ***** TIMER_COUNTER_1 ************** ; TIMSK - Timer/Counter Interrupt Mask Register .equ TICIE1 = 3 ; Timer/Counter1 Input Capture Interrupt Enable .equ OCIE1B = 5 ; Timer/Counter1 Output CompareB Match Interrupt Enable .equ OCIE1A = 6 ; Timer/Counter1 Output CompareA Match Interrupt Enable .equ TOIE1 = 7 ; Timer/Counter1 Overflow Interrupt Enable ; TIFR - Timer/Counter Interrupt Flag register .equ ICF1 = 3 ; Input Capture Flag 1 .equ OCF1B = 5 ; Output Compare Flag 1B .equ OCF1A = 6 ; Output Compare Flag 1A .equ TOV1 = 7 ; Timer/Counter1 Overflow Flag ; TCCR1A - Timer/Counter1 Control Register A .equ WGM10 = 0 ; Pulse Width Modulator Select Bit 0 .equ PWM10 = WGM10 ; For compatibility .equ WGM11 = 1 ; Pulse Width Modulator Select Bit 1 .equ PWM11 = WGM11 ; For compatibility .equ FOC1B = 2 ; Force Output Compare for Channel B .equ FOC1A = 3 ; Force Output Compare for Channel A .equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 .equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 .equ COM1A0 = 6 ; Compare Ouput Mode 1A, bit 0 .equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 ; TCCR1B - Timer/Counter1 Control Register B .equ CS10 = 0 ; Clock Select1 bit 0 .equ CS11 = 1 ; Clock Select1 bit 1 .equ CS12 = 2 ; Clock Select1 bit 2 .equ WGM12 = 3 ; Pulse Width Modulator Select Bit 2 .equ CTC10 = WGM12 ; For compatibility .equ WGM13 = 4 ; Pulse Width Modulator Select Bit 3 .equ CTC11 = WGM13 ; For compatibility .equ ICES1 = 6 ; Input Capture 1 Edge Select .equ ICNC1 = 7 ; Input Capture 1 Noise Canceler ; ***** PORTA ************************ ; PORTA - Port A Data Register .equ PORTA0 = 0 ; Port A Data Register bit 0 .equ PA0 = 0 ; For compatibility .equ PORTA1 = 1 ; Port A Data Register bit 1 .equ PA1 = 1 ; For compatibility .equ PORTA2 = 2 ; Port A Data Register bit 2 .equ PA2 = 2 ; For compatibility .equ PORTA3 = 3 ; Port A Data Register bit 3 .equ PA3 = 3 ; For compatibility .equ PORTA4 = 4 ; Port A Data Register bit 4 .equ PA4 = 4 ; For compatibility .equ PORTA5 = 5 ; Port A Data Register bit 5 .equ PA5 = 5 ; For compatibility .equ PORTA6 = 6 ; Port A Data Register bit 6 .equ PA6 = 6 ; For compatibility .equ PORTA7 = 7 ; Port A Data Register bit 7 .equ PA7 = 7 ; For compatibility ; DDRA - Port A Data Direction Register .equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 .equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 .equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 .equ DDA3 = 3 ; Data Direction Register, Port A, bit 3 .equ DDA4 = 4 ; Data Direction Register, Port A, bit 4 .equ DDA5 = 5 ; Data Direction Register, Port A, bit 5 .equ DDA6 = 6 ; Data Direction Register, Port A, bit 6 .equ DDA7 = 7 ; Data Direction Register, Port A, bit 7 ; PINA - Port A Input Pins .equ PINA0 = 0 ; Input Pins, Port A bit 0 .equ PINA1 = 1 ; Input Pins, Port A bit 1 .equ PINA2 = 2 ; Input Pins, Port A bit 2 .equ PINA3 = 3 ; Input Pins, Port A bit 3 .equ PINA4 = 4 ; Input Pins, Port A bit 4 .equ PINA5 = 5 ; Input Pins, Port A bit 5 .equ PINA6 = 6 ; Input Pins, Port A bit 6 .equ PINA7 = 7 ; Input Pins, Port A bit 7 ; ***** PORTB ************************ ; PORTB - Port B Data Register .equ PORTB0 = 0 ; Port B Data Register bit 0 .equ PB0 = 0 ; For compatibility .equ PORTB1 = 1 ; Port B Data Register bit 1 .equ PB1 = 1 ; For compatibility .equ PORTB2 = 2 ; Port B Data Register bit 2 .equ PB2 = 2 ; For compatibility .equ PORTB3 = 3 ; Port B Data Register bit 3 .equ PB3 = 3 ; For compatibility .equ PORTB4 = 4 ; Port B Data Register bit 4 .equ PB4 = 4 ; For compatibility .equ PORTB5 = 5 ; Port B Data Register bit 5 .equ PB5 = 5 ; For compatibility .equ PORTB6 = 6 ; Port B Data Register bit 6 .equ PB6 = 6 ; For compatibility .equ PORTB7 = 7 ; Port B Data Register bit 7 .equ PB7 = 7 ; For compatibility ; DDRB - Port B Data Direction Register .equ DDB0 = 0 ; Port B Data Direction Register bit 0 .equ DDB1 = 1 ; Port B Data Direction Register bit 1 .equ DDB2 = 2 ; Port B Data Direction Register bit 2 .equ DDB3 = 3 ; Port B Data Direction Register bit 3 .equ DDB4 = 4 ; Port B Data Direction Register bit 4 .equ DDB5 = 5 ; Port B Data Direction Register bit 5 .equ DDB6 = 6 ; Port B Data Direction Register bit 6 .equ DDB7 = 7 ; Port B Data Direction Register bit 7 ; PINB - Port B Input Pins .equ PINB0 = 0 ; Port B Input Pins bit 0 .equ PINB1 = 1 ; Port B Input Pins bit 1 .equ PINB2 = 2 ; Port B Input Pins bit 2 .equ PINB3 = 3 ; Port B Input Pins bit 3 .equ PINB4 = 4 ; Port B Input Pins bit 4 .equ PINB5 = 5 ; Port B Input Pins bit 5 .equ PINB6 = 6 ; Port B Input Pins bit 6 .equ PINB7 = 7 ; Port B Input Pins bit 7 ; ***** PORTC ************************ ; PORTC - Port C Data Register .equ PORTC0 = 0 ; Port C Data Register bit 0 .equ PC0 = 0 ; For compatibility .equ PORTC1 = 1 ; Port C Data Register bit 1 .equ PC1 = 1 ; For compatibility .equ PORTC2 = 2 ; Port C Data Register bit 2 .equ PC2 = 2 ; For compatibility .equ PORTC3 = 3 ; Port C Data Register bit 3 .equ PC3 = 3 ; For compatibility .equ PORTC4 = 4 ; Port C Data Register bit 4 .equ PC4 = 4 ; For compatibility .equ PORTC5 = 5 ; Port C Data Register bit 5 .equ PC5 = 5 ; For compatibility .equ PORTC6 = 6 ; Port C Data Register bit 6 .equ PC6 = 6 ; For compatibility .equ PORTC7 = 7 ; Port C Data Register bit 7 .equ PC7 = 7 ; For compatibility ; DDRC - Port C Data Direction Register .equ DDC0 = 0 ; Port C Data Direction Register bit 0 .equ DDC1 = 1 ; Port C Data Direction Register bit 1 .equ DDC2 = 2 ; Port C Data Direction Register bit 2 .equ DDC3 = 3 ; Port C Data Direction Register bit 3 .equ DDC4 = 4 ; Port C Data Direction Register bit 4 .equ DDC5 = 5 ; Port C Data Direction Register bit 5 .equ DDC6 = 6 ; Port C Data Direction Register bit 6 .equ DDC7 = 7 ; Port C Data Direction Register bit 7 ; PINC - Port C Input Pins .equ PINC0 = 0 ; Port C Input Pins bit 0 .equ PINC1 = 1 ; Port C Input Pins bit 1 .equ PINC2 = 2 ; Port C Input Pins bit 2 .equ PINC3 = 3 ; Port C Input Pins bit 3 .equ PINC4 = 4 ; Port C Input Pins bit 4 .equ PINC5 = 5 ; Port C Input Pins bit 5 .equ PINC6 = 6 ; Port C Input Pins bit 6 .equ PINC7 = 7 ; Port C Input Pins bit 7 ; ***** PORTD ************************ ; PORTD - Port D Data Register .equ PORTD0 = 0 ; Port D Data Register bit 0 .equ PD0 = 0 ; For compatibility .equ PORTD1 = 1 ; Port D Data Register bit 1 .equ PD1 = 1 ; For compatibility .equ PORTD2 = 2 ; Port D Data Register bit 2 .equ PD2 = 2 ; For compatibility .equ PORTD3 = 3 ; Port D Data Register bit 3 .equ PD3 = 3 ; For compatibility .equ PORTD4 = 4 ; Port D Data Register bit 4 .equ PD4 = 4 ; For compatibility .equ PORTD5 = 5 ; Port D Data Register bit 5 .equ PD5 = 5 ; For compatibility .equ PORTD6 = 6 ; Port D Data Register bit 6 .equ PD6 = 6 ; For compatibility .equ PORTD7 = 7 ; Port D Data Register bit 7 .equ PD7 = 7 ; For compatibility ; DDRD - Port D Data Direction Register .equ DDD0 = 0 ; Port D Data Direction Register bit 0 .equ DDD1 = 1 ; Port D Data Direction Register bit 1 .equ DDD2 = 2 ; Port D Data Direction Register bit 2 .equ DDD3 = 3 ; Port D Data Direction Register bit 3 .equ DDD4 = 4 ; Port D Data Direction Register bit 4 .equ DDD5 = 5 ; Port D Data Direction Register bit 5 .equ DDD6 = 6 ; Port D Data Direction Register bit 6 .equ DDD7 = 7 ; Port D Data Direction Register bit 7 ; PIND - Port D Input Pins .equ PIND0 = 0 ; Port D Input Pins bit 0 .equ PIND1 = 1 ; Port D Input Pins bit 1 .equ PIND2 = 2 ; Port D Input Pins bit 2 .equ PIND3 = 3 ; Port D Input Pins bit 3 .equ PIND4 = 4 ; Port D Input Pins bit 4 .equ PIND5 = 5 ; Port D Input Pins bit 5 .equ PIND6 = 6 ; Port D Input Pins bit 6 .equ PIND7 = 7 ; Port D Input Pins bit 7 ; ***** PORTE ************************ ; PORTE - Port E Data Register .equ PORTE0 = 0 ; .equ PE0 = 0 ; For compatibility .equ PORTE1 = 1 ; .equ PE1 = 1 ; For compatibility .equ PORTE2 = 2 ; .equ PE2 = 2 ; For compatibility ; DDRE - Port E Data Direction Register .equ DDE0 = 0 ; .equ DDE1 = 1 ; .equ DDE2 = 2 ; ; PINE - Port E Input Pins .equ PINE0 = 0 ; .equ PINE1 = 1 ; .equ PINE2 = 2 ; ; ***** EEPROM *********************** ; EEDR - EEPROM Data Register .equ EEDR0 = 0 ; EEPROM Data Register bit 0 .equ EEDR1 = 1 ; EEPROM Data Register bit 1 .equ EEDR2 = 2 ; EEPROM Data Register bit 2 .equ EEDR3 = 3 ; EEPROM Data Register bit 3 .equ EEDR4 = 4 ; EEPROM Data Register bit 4 .equ EEDR5 = 5 ; EEPROM Data Register bit 5 .equ EEDR6 = 6 ; EEPROM Data Register bit 6 .equ EEDR7 = 7 ; EEPROM Data Register bit 7 ; EECR - EEPROM Control Register .equ EERE = 0 ; EEPROM Read Enable .equ EEWE = 1 ; EEPROM Write Enable .equ EEMWE = 2 ; EEPROM Master Write Enable .equ EEWEE = EEMWE ; For compatibility .equ EERIE = 3 ; EEPROM Ready Interrupt Enable ; ***** LOCKSBITS ******************************************************** .equ LB1 = 0 ; Lock bit .equ LB2 = 1 ; Lock bit .equ BLB01 = 2 ; Boot Lock bit .equ BLB02 = 3 ; Boot Lock bit .equ BLB11 = 4 ; Boot lock bit .equ BLB12 = 5 ; Boot lock bit ; ***** FUSES ************************************************************ ; LOW fuse bits .equ CKSEL0 = 0 ; Select Clock Source .equ CKSEL1 = 1 ; Select Clock Source .equ CKSEL2 = 2 ; Select Clock Source .equ CKSEL3 = 3 ; Select Clock Source .equ SUT0 = 4 ; Select start-up time .equ SUT1 = 5 ; Select start-up time .equ BODEN = 6 ; Brown out detector enable .equ BODLEVEL = 7 ; Brown out detector trigger level ; HIGH fuse bits .equ BOOTRST = 0 ; Select Reset Vector .equ BOOTSZ0 = 1 ; Select Boot Size .equ BOOTSZ1 = 2 ; Select Boot Size .equ EESAVE = 3 ; EEPROM memory is preserved through chip erase .equ CKOPT = 4 ; Oscillator Options .equ SPIEN = 5 ; Enable Serial programming and Data Downloading .equ WDTON = 6 ; Watchdog timer always on .equ S8515C = 7 ; AT90S4414/8515 compabillity mode ; ***** CPU REGISTER DEFINITIONS ***************************************** .def XH = r27 .def XL = r26 .def YH = r29 .def YL = r28 .def ZH = r31 .def ZL = r30 ; ***** DATA MEMORY DECLARATIONS ***************************************** .equ FLASHEND = 0x0fff ; Note: Word address .equ IOEND = 0x003f .equ SRAM_START = 0x0060 .equ SRAM_SIZE = 512 .equ RAMEND = 0x025f .equ XRAMEND = 0xffff .equ E2END = 0x01ff .equ EEPROMEND = 0x01ff .equ EEADRBITS = 9 #pragma AVRPART MEMORY PROG_FLASH 8192 #pragma AVRPART MEMORY EEPROM 512 #pragma AVRPART MEMORY INT_SRAM SIZE 512 #pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60 ; ***** BOOTLOADER DECLARATIONS ****************************************** .equ NRWW_START_ADDR = 0xc00 .equ NRWW_STOP_ADDR = 0xfff .equ RWW_START_ADDR = 0x0 .equ RWW_STOP_ADDR = 0xbff .equ PAGESIZE = 32 .equ FIRSTBOOTSTART = 0xf80 .equ SECONDBOOTSTART = 0xf00 .equ THIRDBOOTSTART = 0xe00 .equ FOURTHBOOTSTART = 0xc00 .equ SMALLBOOTSTART = FIRSTBOOTSTART .equ LARGEBOOTSTART = FOURTHBOOTSTART ; ***** INTERRUPT VECTORS ************************************************ .equ INT0addr = 0x0001 ; External Interrupt Request 0 .equ INT1addr = 0x0002 ; External Interrupt Request 1 .equ ICP1addr = 0x0003 ; Timer/Counter1 Capture Event .equ OC1Aaddr = 0x0004 ; Timer/Counter1 Compare Match A .equ OC1Baddr = 0x0005 ; Timer/Counter1 Compare MatchB .equ OVF1addr = 0x0006 ; Timer/Counter1 Overflow .equ OVF0addr = 0x0007 ; Timer/Counter0 Overflow .equ SPIaddr = 0x0008 ; Serial Transfer Complete .equ URXCaddr = 0x0009 ; USART, Rx Complete .equ UDREaddr = 0x000a ; USART Data Register Empty .equ UTXCaddr = 0x000b ; USART, Tx Complete .equ ACIaddr = 0x000c ; Analog Comparator .equ INT2addr = 0x000d ; External Interrupt Request 2 .equ OC0addr = 0x000e ; Timer 0 Compare Match .equ ERDYaddr = 0x000f ; EEPROM Ready .equ SPMRaddr = 0x0010 ; Store Program Memory Ready .equ INT_VECTORS_SIZE = 17 ; size in words #pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break #endif /* _M8515DEF_INC_ */ ; ***** END OF FILE ******************************************************