INTRO
=====

DP_POT.DLL  
IS A 4 POT {FOR NOW} 8 BIT WIDE PDRC  
{PROGRAMMABLE DIGITIZED RESISTANCE CONVERTER}

AN RDAC IN ESSACE WITH NO A-D SECTIONS IN THE FORM OF R2R 
TO FORM A SELECTABLE SCALABLE DIGITAL POTS ARRAY
WILL ALLOW UP TO 16 32 BIT POTS EVENTUALY
WITH 32 BIT 16 BIT 8 BIT AND 4 BIT BUSABLE PROGRAMMING 

NO SUB MODELS ARE USED TO ACHIEVE THE POTS SPREAD 
AND DEBUG INFO IN GIVEN IN OHMS  
ROUNDED TO THE NEARSET STEPPING {IE  POTVAL /256{8BIT} IS SINGLE STEP}

THERE IS A HOLD FUNCTION AND ALSO A LOAD  
SO A HELD VALUE CAN BE JAMMED FURTHER THEN RELOADED 

THERE IS A RESET ALSO SETS ALL POTS ONE ENDED 



have a play around with it's designs etc... 
and yes there are heeps better systems for the code
but i prefer to get something working then worry about nice code


ILL ADD TO THE MODEL AS TIME ALLOWS 
FOR NOW THIS IS ALPHA RELEASE V1.02

ADDITIONS OF FUNCTIONS 
=======================
Added 16 pot isis part {still working coding its bus etc...}
added too the status popup etc...

BUGS CLOSED
-----------
v1.02 ALPHA
reworked all pins and dll code to add bus pins 
16 pot part now runs fine
lots more parts to make to fill the library up
closed a few bugs and reworked the fifo loader using bus pin calls instead of dsimpin
seems a little faster now...!
//////////////////////////////////////////////////////////////////////
v1.01 ALPHA
fixed several bugs in the menus adding more properties
and code for the 16 bit bus addition's
added xpots setting to allow for upto 16 pots @ 16bit 
planned to add 32 bit addressing
//////////////////////////////////////////////////////////////////////
v1.0 ALPHA POST INITIAL RELEASE 
fixed bug  when loading pots from a pause to sim cycle
	  	bug was that pots would zero then load 
fixed bug wrong maths divisor for pot steppings 
//////////////////////////////////////////////////////////////////////

WHAT IN THE NEXT RELEASE
=========================
V1.03 ALPHA 

bug identified in singualr matrix error within v6.9 & greater.............inprogress
previous versions are ok

WILL CONTAIN BUG FIX'S TO THE MATHS TO CORRECT THE POTS ALLIGNMENT 
WILL SHOW UP BETTER IN 16 AND 32 BIT MODES AS THE GRANULARITY INCREASES
ILL THINK UP A BETTER SET OF EQUASIONS FOR LOADING THE RESISTOR VALUES.....inprogress

ILL ADD ADJUSTABLE BIT CONVERSION SIZES {BTE PROPERTY}.....................DONE
ILL BUILD AN ACTIVE MODEL FRAMEWORK ROUND THE PART ........................inprogress
TOO OPEN IT UP AND ADD SOME METERS  ON THE ACTUAL PART ON THE SHEET

ILL ADD MATHS  FOR LOG AND LINEAR TAPPERS..................................inprogress
ADDING GEARTH INTO IT ALSO TO CLEAN ANY ISIS ERRORS SHOWN IN THE LOG

WILL ADD A SHDN PIN  THAT ALLOWS FOR l->W GOES SHORT AND W->H GOES TO A SETTABLE MAXIMUM 
AS PER R2R TYPE DIGITAL POTS RDAC
SO THIS CAN BE USED AS A PRIMITIVE PART....................................inprogress

ILL ADD ANOTHER SET OF SELECTOR PINS TO CHOOSE THE ACTIVE BUS
AND ALSO A SERIAL OUTPUT PIN SO EEPROMS ETC CAN BE ADDED 
MAYBE I2C ADDRESSING FOR STORAGE ETC... ...................................inprogress


NOTES:
-------
if your using v6.9  tough you cant use this primitive yet
till i clear off the error in the matrix {singular matrix error}
i realised this error is there just v6.9> is more sensative to this type of
itteration and ill fix this next....


THE READOUT OF THE STATUS POPUP SHOWS TWO READINGS
POT END TO END RESISTANCE & POT lOW PIN {CCW FULLY} TO THE WIPER  RESISTANCE  
I THINK THIS IS THE MOST HANDY ONE OF THE TWO 
======================================================
MAREADOUT.DLL & VDDCOMMON.LML 
youll need also SLDVDD from my comvdd site
to run the designs
http://uk.geocities.com/vsmvdd/
are needed for the test design to run ok
if you have these already 
youll find these two files are the latest versions
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