library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity top_memory is
Port ( clk : in STD_LOGIC;
leer : in STD_LOGIC;
direccion : in STD_LOGIC_VECTOR (3 downto 0);
entrada : in STD_LOGIC_VECTOR (3 downto 0);
salida : out STD_LOGIC_VECTOR (3 downto 0));
end top_memory;
architecture Behavioral of top_memory is
-- The following code must appear in the VHDL architecture header:
component memory
port (
addr: IN std_logic_VECTOR(3 downto 0);
clk: IN std_logic;
din: IN std_logic_VECTOR(3 downto 0);
dout: OUT std_logic_VECTOR(3 downto 0);
we: IN std_logic);
end component;
begin
instancia : memory
port map (
addr => direccion,
clk => clk,
din => entrada,
dout => salida,
we => leer);
end Behavioral;