LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY pap IS
PORT(w, clk :IN STD_LOGIC;
Q :OUT STD_LOGIC_VECTOR(1 TO 4));
END pap;
ARCHITECTURE secuencia OF pap IS
BEGIN
PROCESS(clk)
VARIABLE Sreg : STD_LOGIC_VECTOR(1 TO 4);
BEGIN
IF Clk'EVENT AND Clk = '1' THEN
Sreg(4):= w;
Sreg(3):= Sreg(4);
Sreg(2):= Sreg(3);
Sreg(1):= Sreg(2);
END IF;
Q<= Sreg;
END PROCESS;
END secuencia;