unsigned portCHAR cSpiReadWrite(pSpiRWdata pData)
{
unsigned portCHAR errCode;
volatile int nRDR;
unsigned portCHAR bHoldCS = 0;
if (pData->holdCS) {bHoldCS = AT91C_SPI_CSAAT;}
/*Configure for the selected Chip Select, the clock phase, bits per transfer, baud rate and
if Chip Select Active After Transfer
*/
AT91F_SPI_CfgCs(AT91C_BASE_SPI, pData->device, AT91C_SPI_CPOL | AT91C_SPI_BITS_8 | (pData->clockDivider << 8) | (bHoldCS));
/*Open the PDC module*/
AT91F_PDC_Open(AT91C_BASE_PDC_SPI);
/*Disable Spi activity during PDC initialization*/
AT91F_PDC_DisableRx(AT91C_BASE_PDC_SPI);
AT91F_PDC_DisableTx(AT91C_BASE_PDC_SPI);
/*Has bytes to write*/
if (pData->sizeW == 0)
{
AT91F_SPI_SendFrame (AT91C_BASE_SPI, (char *) pData->dataR, pData->sizeR, 0, 0);
}
else
{
AT91F_SPI_SendFrame (AT91C_BASE_SPI, (char *) pData->dataW, pData->sizeW, 0, 0);
}
/*Has bytes to read*/
if (pData->sizeR > 0)
{
AT91F_SPI_ReceiveFrame (AT91C_BASE_SPI, (char*) pData->dataR, pData->sizeR, 0, 0);
AT91F_PDC_EnableRx (AT91C_BASE_PDC_SPI);
}
/*Enable Transmission*/
AT91F_PDC_EnableTx(AT91C_BASE_PDC_SPI);
/*Configure and enable interrupts*/
//AT91F_AIC_ConfigureIt(AT91C_BASE_AIC, AT91C_ID_SPI, AT91C_AIC_PRIOR_LOWEST + 1, AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, ( void (*)(void) ) vSpiISREntry);
//AT91F_AIC_EnableIt(AT91C_BASE_AIC, AT91C_ID_SPI);
/*Test: wait to complete*/
while ((AT91C_BASE_SPI->SPI_SR & AT91C_SPI_TXBUFE) == 0 || (AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RXBUFF) == 0);
AT91F_PDC_Close (AT91C_BASE_PDC_SPI);
/* Flush SPI RDR buffer (in case there is pending data)*/
nRDR = AT91F_SPI_GetChar (AT91C_BASE_SPI);
return errCode;
}