-- Declaracion de librerias
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Declaracion de la entidad ---
entity NiosII is
Port (
CLK_i : in std_logic;
RESET_i: in std_logic;
PORT_o : out std_logic_vector (7 downto 0); -- Se declara la salida
ADDR_SDRAM_o : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
BA_SDRAM_o : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
CAS_SDRAM_o : OUT STD_LOGIC;
CKE_SDRAM_o : OUT STD_LOGIC;
CS_SDRAM_o : OUT STD_LOGIC;
DQ_SDRAM_io : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0);
DQM_SDRAM_o : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
RAS_SDRAM_o : OUT STD_LOGIC;
WE_SDRAM_o : OUT STD_LOGIC;
CLK_SDRAM_o: OUT STD_LOGIC
);
end NiosII;
architecture behavior of NiosII is
component altpll0 is
port(
inclk0 : IN STD_LOGIC;
c0 : OUT STD_LOGIC;
c1 : OUT STD_LOGIC
);
end component altpll0;
component SkuP is
port(
-- 1) global signals:
signal clk_0 : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
-- the_pio
signal out_port_from_the_pio : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
-- the_sdram
signal zs_addr_from_the_sdram : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
signal zs_ba_from_the_sdram : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal zs_cas_n_from_the_sdram : OUT STD_LOGIC;
signal zs_cke_from_the_sdram : OUT STD_LOGIC;
signal zs_cs_n_from_the_sdram : OUT STD_LOGIC;
signal zs_dq_to_and_from_the_sdram : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0);
signal zs_dqm_from_the_sdram : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
signal zs_ras_n_from_the_sdram : OUT STD_LOGIC;
signal zs_we_n_from_the_sdram : OUT STD_LOGIC
);
end component SkuP;
signal sgCLK_uP: std_logic;
begin
U0: altpll0 port map(
inclk0 => CLK_i,
c0 => CLK_SDRAM_o,
c1 => sgCLK_uP
);
U1: SkuP port map(
clk_0 => sgCLK_uP, -- 50 MHZ del PLL.-
reset_n => RESET_i, -- Switch para resetear.-
out_port_from_the_pio => PORT_o, -- Salida, PIO.-
zs_addr_from_the_sdram => ADDR_SDRAM_o,
zs_ba_from_the_sdram => BA_SDRAM_o,
zs_cas_n_from_the_sdram => CAS_SDRAM_o,
zs_cke_from_the_sdram => CKE_SDRAM_o,
zs_cs_n_from_the_sdram => CS_SDRAM_o,
zs_dq_to_and_from_the_sdram => DQ_SDRAM_io,
zs_dqm_from_the_sdram => DQM_SDRAM_o,
zs_ras_n_from_the_sdram => RAS_SDRAM_o,
zs_we_n_from_the_sdram => WE_SDRAM_o
);
end architecture;