// INTCON: REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)
INTCON = (unsigned char)
+(1<<7) // GIE: Global Interrupt Enable bit
// 1 = Enables all unmasked interrupts
// 0 = Disables all interrupts
+(0<<6) // PEIE: Peripheral Interrupt Enable bit
// 1 = Enables all unmasked peripheral interrupts
// 0 = Disables all peripheral interrupts
+(0<<5) // TMR0IE: TMR0 Overflow Interrupt Enable bit
// 1 = Enables the TMR0 interrupt
// 0 = Disables the TMR0 interrupt
+(0<<4) // INTE: RB0/INT External Interrupt Enable bit
// 1 = Enables the RB0/INT external interrupt
// 0 = Disables the RB0/INT external interrupt
+(1<<3) // RBIE: RB Port Change Interrupt Enable bit
// 1 = Enables the RB port change interrupt
// 0 = Disables the RB port change interrupt
+(0<<2) // TMR0IF: TMR0 Overflow Interrupt Flag bit
// 1 = TMR0 register has overflowed (must be cleared in software)
// 0 = TMR0 register did not overflow
+(0<<1) // INTF: RB0/INT External Interrupt Flag bit
// 1 = The RB0/INT external interrupt occurred (must be cleared
// in software)
// 0 = The RB0/INT external interrupt did not occur
+(0); // RBIF: RB Port Change Interrupt Flag bit
// 1 = At least one of the RB7:RB4 pins changed state; a
// mismatch condition will continue to set the bit. Reading
// PORTB will end the mismatch condition and allow the bit
// to be cleared (must be cleared in software).
// 0 = None of the RB7:RB4 pins have changed state
INTCON = 0b10001000;
// INTCON: REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)
INTCON = (unsigned char)
+(0<<7) // GIE: Global Interrupt Enable bit
// 1 = Enables all unmasked interrupts
// 0 = Disables all interrupts
+(0<<6) // PEIE: Peripheral Interrupt Enable bit
// 1 = Enables all unmasked peripheral interrupts
// 0 = Disables all peripheral interrupts
+(0<<5) // TMR0IE: TMR0 Overflow Interrupt Enable bit
// 1 = Enables the TMR0 interrupt
// 0 = Disables the TMR0 interrupt
+(0<<4) // INTE: RB0/INT External Interrupt Enable bit
// 1 = Enables the RB0/INT external interrupt
// 0 = Disables the RB0/INT external interrupt
+(0<<3) // RBIE: RB Port Change Interrupt Enable bit
// 1 = Enables the RB port change interrupt
// 0 = Disables the RB port change interrupt
+(0<<2) // TMR0IF: TMR0 Overflow Interrupt Flag bit
// 1 = TMR0 register has overflowed (must be cleared in software)
// 0 = TMR0 register did not overflow
+(0<<1) // INTF: RB0/INT External Interrupt Flag bit
// 1 = The RB0/INT external interrupt occurred (must be cleared
// in software)
// 0 = The RB0/INT external interrupt did not occur
+(0); // RBIF: RB Port Change Interrupt Flag bit
// 1 = At least one of the RB7:RB4 pins changed state; a
// mismatch condition will continue to set the bit. Reading
// PORTB will end the mismatch condition and allow the bit
// to be cleared (must be cleared in software).
// 0 = None of the RB7:RB4 pins have changed state
// T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)
T1CON = (unsigned char)
+(0<<6) // Unimplemented: Read as ‘0’
+(0<<4) // T1CKPS: Timer1 Input Clock Prescale Select bits
// 3 = 1:8 prescale value
// 2 = 1:4 prescale value
// 1 = 1:2 prescale value
// 0 = 1:1 prescale value
+(0<<3) // T1OSCEN: Timer1 Oscillator Enable Control bit
// 1 = Oscillator is enabled
// 0 = Oscillator is shut-off (the oscillator inverter is turned
// off to eliminate power drain)
+(0<<2) // T1SYNC: Timer1 External Clock Input Synchronization Control bit
// When TMR1CS = 1:
// 1 = Do not synchronize external clock input
// 0 = Synchronize external clock input When TMR1CS = 0: This
// bit is ignored. Timer1 uses the internal clock when
// TMR1CS = 0.
+(0<<1) // TMR1CS: Timer1 Clock Source Select bit
// 1 = External clock from pin RC0/T1OSO/T1CKI (on the rising
// edge)
// 0 = Internal clock (FOSC/4)
+(0); // TMR1ON: Timer1 On bit
// 1 = Enables Timer1
// 0 = Stops Timer1
// CCP1CON: REGISTER/CCP2CON REGISTER (ADDRESS 17h/1Dh)
CCP1CON = (unsigned char)
+(0<<6) // Unimplemented: Read as ‘0’
+(0<<4) // CCPxX:CCPxY: PWM Least Significant bits Capture mode: Unused.
// Compare mode: Unused. PWM mode: These bits are the two
// LSbs of the PWM duty cycle. The eight MSbs are found in
// CCPRxL.
+(0); // CCPxM: CCPx Mode Select bits
// 0 = Capture/Compare/PWM disabled (resets CCPx module)
// 4 = Capture mode, every falling edge
// 5 = Capture mode, every rising edge
// 6 = Capture mode, every 4th rising edge
// 7 = Capture mode, every 16th rising edge
// 8 = Compare mode, set output on match (CCPxIF bit is set)
// 9 = Compare mode, clear output on match (CCPxIF bit is set)
// 10 = Compare mode, generate software interrupt on match
// (CCPxIF bit is set, CCPx pin is unaffected)
// 11 = Compare mode, trigger special event (CCPxIF bit is set,
// CCPx pin is unaffected); CCP1 resets TMR1; CCP2 resets
// TMR1 and starts an A/D conversion (if A/D module is
// enabled) 11xx = PWM mode
REGISTER 2-3: INTCON REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF
bit 7 bit 0
bit 7 GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4 INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3 RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1 INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0 RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 pins changed state; a mismatch condition will continue to set
the bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared
(must be cleared in software).
0 = None of the RB7:RB4 pins have changed state
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
REGISTER 6-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 7 bit 0
bit 7-6 Unimplemented: Read as ‘0’
bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11 = 1:8 prescale value
10 = 1:4 prescale value
01 = 1:2 prescale value
00 = 1:1 prescale value
bit 3 T1OSCEN: Timer1 Oscillator Enable Control bit
1 = Oscillator is enabled
0 = Oscillator is shut-off (the oscillator inverter is turned off to eliminate power drain)
bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit
When TMR1CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1 TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0 TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
REGISTER 8-1: CCP1CON REGISTER/CCP2CON REGISTER (ADDRESS 17h/1Dh)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — CCPxX CCPxY CCPxM3 CCPxM2 CCPxM1 CCPxM0
bit 7 bit 0
bit 7-6 Unimplemented: Read as ‘0’
bit 5-4 CCPxX:CCPxY: PWM Least Significant bits
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
bit 3-0 CCPxM3:CCPxM0: CCPx Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCPx module)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (CCPxIF bit is set)
1001 = Compare mode, clear output on match (CCPxIF bit is set)
1010 = Compare mode, generate software interrupt on match (CCPxIF bit is set, CCPx pin is
unaffected)
1011 = Compare mode, trigger special event (CCPxIF bit is set, CCPx pin is unaffected); CCP1
resets TMR1; CCP2 resets TMR1 and starts an A/D conversion (if A/D module is
enabled)
11xx = PWM mode
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown