/*
* File: mainpruebas2.c
* Author: l
*
* Created on July 7, 2015, 1:32 PM
*/
// #pragma config statements should precede project file includes.
// Use project enums instead of #define for ON and OFF.
// CONFIG1H
#pragma config OSC = HS // Oscillator Selection bits (HS oscillator)
#pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
#pragma config IESO = OFF // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)
// CONFIG2L
#pragma config PWRT = ON // Power-up Timer Enable bit (PWRT enabled)
#pragma config BOREN = SBORDIS // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled))
#pragma config BORV = 3 // Brown Out Reset Voltage bits (Minimum setting)
// CONFIG2H
#pragma config WDT = OFF // Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))
#pragma config WDTPS = 32768 // Watchdog Timer Postscale Select bits (1:32768)
// CONFIG3H
#pragma config CCP2MX = PORTC // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
#pragma config PBADEN = OFF // PORTB A/D Enable bit (PORTB<4:0> pins are configured as analog input channels on Reset)
#pragma config LPT1OSC = OFF // Low-Power Timer1 Oscillator Enable bit (Timer1 configured for higher power operation)
#pragma config MCLRE = ON // MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled)
// CONFIG4L
#pragma config STVREN = ON // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
#pragma config LVP = ON // Single-Supply ICSP Enable bit (Single-Supply ICSP enabled)
#pragma config XINST = OFF // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))
// CONFIG5L
#pragma config CP0 = OFF // Code Protection bit (Block 0 (000800-003FFFh) not code-protected)
#pragma config CP1 = OFF // Code Protection bit (Block 1 (004000-007FFFh) not code-protected)
#pragma config CP2 = OFF // Code Protection bit (Block 2 (008000-00BFFFh) not code-protected)
#pragma config CP3 = OFF // Code Protection bit (Block 3 (00C000-00FFFFh) not code-protected)
// CONFIG5H
#pragma config CPB = OFF // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected)
#pragma config CPD = OFF // Data EEPROM Code Protection bit (Data EEPROM not code-protected)
// CONFIG6L
#pragma config WRT0 = OFF // Write Protection bit (Block 0 (000800-003FFFh) not write-protected)
#pragma config WRT1 = OFF // Write Protection bit (Block 1 (004000-007FFFh) not write-protected)
#pragma config WRT2 = OFF // Write Protection bit (Block 2 (008000-00BFFFh) not write-protected)
#pragma config WRT3 = OFF // Write Protection bit (Block 3 (00C000-00FFFFh) not write-protected)
// CONFIG6H
#pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
#pragma config WRTB = OFF // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected)
#pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM not write-protected)
// CONFIG7L
#pragma config EBTR0 = OFF // Table Read Protection bit (Block 0 (000800-003FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR1 = OFF // Table Read Protection bit (Block 1 (004000-007FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR2 = OFF // Table Read Protection bit (Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks)
#pragma config EBTR3 = OFF // Table Read Protection bit (Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks)
// CONFIG7H
#pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks)
#include <xc.h>
#include <stdio.h>
#include <stdlib.h>
#define _XTAL_FREQ 20000000
#define __delay_ms(x) _delay((unsigned long)((x)*(_XTAL_FREQ/20000000.0)))
void main ()
{
TRISB = 0b00000000; // Configuro puerto B como salidas
while (1) // Bucle infinito
{
PORTBbits.RB1 = 0; // Apago pin RB0
__delay_ms(500);
PORTBbits.RB1 = 1; // Enciendo pin RB0
__delay_ms(500);
}
}
/*
* File: mainpruebas2.c
* Author: l
*
* Created on July 7, 2015, 1:32 PM
*/
// #pragma config statements should precede project file includes.
// Use project enums instead of #define for ON and OFF.
// CONFIG1H
#pragma config OSC = HS // Oscillator Selection bits (HS oscillator)
#pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
#pragma config IESO = OFF // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)
// CONFIG2L
#pragma config PWRT = ON // Power-up Timer Enable bit (PWRT enabled)
#pragma config BOREN = SBORDIS // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled))
#pragma config BORV = 3 // Brown Out Reset Voltage bits (Minimum setting)
// CONFIG2H
#pragma config WDT = OFF // Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))
#pragma config WDTPS = 32768 // Watchdog Timer Postscale Select bits (1:32768)
// CONFIG3H
#pragma config CCP2MX = PORTC // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
#pragma config PBADEN = OFF // PORTB A/D Enable bit (PORTB<4:0> pins are configured as analog input channels on Reset)
#pragma config LPT1OSC = OFF // Low-Power Timer1 Oscillator Enable bit (Timer1 configured for higher power operation)
#pragma config MCLRE = ON // MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled)
// CONFIG4L
#pragma config STVREN = ON // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
#pragma config LVP = ON // Single-Supply ICSP Enable bit (Single-Supply ICSP enabled)
#pragma config XINST = OFF // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))
// CONFIG5L
#pragma config CP0 = OFF // Code Protection bit (Block 0 (000800-003FFFh) not code-protected)
#pragma config CP1 = OFF // Code Protection bit (Block 1 (004000-007FFFh) not code-protected)
#pragma config CP2 = OFF // Code Protection bit (Block 2 (008000-00BFFFh) not code-protected)
#pragma config CP3 = OFF // Code Protection bit (Block 3 (00C000-00FFFFh) not code-protected)
// CONFIG5H
#pragma config CPB = OFF // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected)
#pragma config CPD = OFF // Data EEPROM Code Protection bit (Data EEPROM not code-protected)
// CONFIG6L
#pragma config WRT0 = OFF // Write Protection bit (Block 0 (000800-003FFFh) not write-protected)
#pragma config WRT1 = OFF // Write Protection bit (Block 1 (004000-007FFFh) not write-protected)
#pragma config WRT2 = OFF // Write Protection bit (Block 2 (008000-00BFFFh) not write-protected)
#pragma config WRT3 = OFF // Write Protection bit (Block 3 (00C000-00FFFFh) not write-protected)
// CONFIG6H
#pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
#pragma config WRTB = OFF // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected)
#pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM not write-protected)
// CONFIG7L
#pragma config EBTR0 = OFF // Table Read Protection bit (Block 0 (000800-003FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR1 = OFF // Table Read Protection bit (Block 1 (004000-007FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR2 = OFF // Table Read Protection bit (Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks)
#pragma config EBTR3 = OFF // Table Read Protection bit (Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks)
// CONFIG7H
#pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks)
#include <xc.h>
#include <pic18f4620.h>
//#include <delays.h>
#include <stdio.h>
#include <stdlib.h>
#define _XTAL_FREQ 20000000
#define __delay_ms(x) _delay((unsigned long)((x)*(_XTAL_FREQ/20000000.0)))
void main ()
{
TRISB = 0b00000000; // Configuro puerto B como salidas
while (1) // Bucle infinito
{
LATBbits.LB1 = 0; // Apago pin RB0
__delay_ms(500);
LATBbits.LB1 = 1; // Enciendo pin RB0
__delay_ms(500);
}
}
Target halted. Stopwatch cycle count = 2505012 (501,0024 ms)Entonces probe con 1 delay menos y termine con
Target halted. Stopwatch cycle count = 2500002 (500,0004 ms)Si supongo el maximo de 65k (2^16) El maximo tiempo que puedo hacer una demora con ese oscilador es de 13ms :/
Target halted. Stopwatch cycle count = 2500258 (500,0516 ms)
:: advisory: (1233) Employing 18F4620 errata work-arounds:
:: advisory: (1234) * Corrupted fast interrupt shadow registers
:: advisory: (1234) * Data in RAM location can be corrupted if async. reset occurs during write
Target halted. Stopwatch cycle count = 2500108 (500,0216 ms)
Lo que no entiendo es por que esta tan limitada, no se si sera por el tema de que el cristal esta a 20Mhzen efecto amigo si funciona, un saludo y agradecimiento
La funcion __delay_ms() ya se encuentra definida en "xc.h" asi que no hay necesidad de hacerlo de nuevo. Probe con el __delay_ms(500) y me dijo que era un argumento demasiado grande.
Imagino esto por que debe usar la funcion delay __delay() y este debe tener un numero maximo. Y si quisiera calcula la cantidad de ciclos a meter para 500ms serian:
500ms / (4/Fosc) = 2.500.000 ciclos.... y se necesitarian casi 24 bits para eso,y creo que le maximo es de 16 bits o 65535(Abajo digo cuales son los limites). Entonces intente hacer 500 delays de 1ms, y ahi me funciono.Código: C
#include <xc.h> #include <stdint.h> /* Includes uint16_t definition */ #include <stdbool.h> /* Includes true/false definition */ #define _XTAL_FREQ 20000000 void main() { uint16_t i; TRISB = 0b00000000; // Configuro puerto B como salidas while (1) // Bucle infinito { LATBbits.LB1 = 0; // Apago pin RB0 for(i=0;i<499;i++) { __delay_ms(1); } LATBbits.LB1 = 1; // Enciendo pin RB0 for(i=0;i<499;i++) { __delay_ms(1); } } }
Tampoco pongo el .h del pic, ya que tambien se encuentra incluido por el compilador al elegirlo. Y la configuracion la tengo en otro archivo.
Culpa de de ese bucle si ponia (i < 500) en el for, terminaba durando:CitarTarget halted. Stopwatch cycle count = 2505012 (501,0024 ms)Entonces probe con 1 delay menos y termine conCitarTarget halted. Stopwatch cycle count = 2500002 (500,0004 ms)Si supongo el maximo de 65k (2^16) El maximo tiempo que puedo hacer una demora con ese oscilador es de 13ms :/
Asi que probe con:Código: CY obtuve:
for(i=0;i<50;i++) { __delay_ms(10); }CitarTarget halted. Stopwatch cycle count = 2500258 (500,0516 ms)
Pero lo que mas me llamo la atencion fue esto:Citar:: advisory: (1233) Employing 18F4620 errata work-arounds:
:: advisory: (1234) * Corrupted fast interrupt shadow registers
:: advisory: (1234) * Data in RAM location can be corrupted if async. reset occurs during write
********** EDIT **********
Buscando info por internet me encuentro que es distinto para PIC18 y para PIC16.
PIC16 , el maximo son 50.462.464 ciclos
PIC18 , el maximo es de 197.120 ciclos
Asi que el maximo delay que podes generar es de 197120 * Tcy = 39ms con ese cristal de 20Mhz, de intentar generar un valor mas grande, o repetis o usar un for.
Probado conCódigo: CResultado
for(i=0;i<20;i++) { __delay_ms(25); }CitarTarget halted. Stopwatch cycle count = 2500108 (500,0216 ms)