// PIC18F45K22 Configuration Bit Settings
// 'C' source line config statements
#include <xc.h>
// #pragma config statements should precede project file includes.
// Use project enums instead of #define for ON and OFF.
// CONFIG1H
#pragma config FOSC = INTIO67 // Oscillator Selection bits (Internal oscillator block)
#pragma config PLLCFG = OFF // 4X PLL Enable (Oscillator used directly)
#pragma config PRICLKEN = ON // Primary clock enable bit (Primary clock is always enabled)
#pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
#pragma config IESO = OFF // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)
// CONFIG2L
#pragma config PWRTEN = OFF // Power-up Timer Enable bit (Power up timer disabled)
#pragma config BOREN = SBORDIS // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled))
#pragma config BORV = 190 // Brown Out Reset Voltage bits (VBOR set to 1.90 V nominal)
// CONFIG2H
#pragma config WDTEN = ON // Watchdog Timer Enable bits (WDT is always enabled. SWDTEN bit has no effect)
#pragma config WDTPS = 32768 // Watchdog Timer Postscale Select bits (1:32768)
// CONFIG3H
#pragma config CCP2MX = PORTC1 // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
#pragma config PBADEN = ON // PORTB A/D Enable bit (PORTB<5:0> pins are configured as analog input channels on Reset)
#pragma config CCP3MX = PORTB5 // P3A/CCP3 Mux bit (P3A/CCP3 input/output is multiplexed with RB5)
#pragma config HFOFST = ON // HFINTOSC Fast Start-up (HFINTOSC output and ready status are not delayed by the oscillator stable status)
#pragma config T3CMX = PORTC0 // Timer3 Clock input mux bit (T3CKI is on RC0)
#pragma config P2BMX = PORTD2 // ECCP2 B output mux bit (P2B is on RD2)
#pragma config MCLRE = EXTMCLR // MCLR Pin Enable bit (MCLR pin enabled, RE3 input pin disabled)
// CONFIG4L
#pragma config STVREN = ON // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
#pragma config LVP = ON // Single-Supply ICSP Enable bit (Single-Supply ICSP enabled if MCLRE is also 1)
#pragma config XINST = OFF // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))
// CONFIG5L
#pragma config CP0 = OFF // Code Protection Block 0 (Block 0 (000800-001FFFh) not code-protected)
#pragma config CP1 = OFF // Code Protection Block 1 (Block 1 (002000-003FFFh) not code-protected)
#pragma config CP2 = OFF // Code Protection Block 2 (Block 2 (004000-005FFFh) not code-protected)
#pragma config CP3 = OFF // Code Protection Block 3 (Block 3 (006000-007FFFh) not code-protected)
// CONFIG5H
#pragma config CPB = OFF // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected)
#pragma config CPD = OFF // Data EEPROM Code Protection bit (Data EEPROM not code-protected)
// CONFIG6L
#pragma config WRT0 = OFF // Write Protection Block 0 (Block 0 (000800-001FFFh) not write-protected)
#pragma config WRT1 = OFF // Write Protection Block 1 (Block 1 (002000-003FFFh) not write-protected)
#pragma config WRT2 = OFF // Write Protection Block 2 (Block 2 (004000-005FFFh) not write-protected)
#pragma config WRT3 = OFF // Write Protection Block 3 (Block 3 (006000-007FFFh) not write-protected)
// CONFIG6H
#pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
#pragma config WRTB = OFF // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected)
#pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM not write-protected)
// CONFIG7L
#pragma config EBTR0 = OFF // Table Read Protection Block 0 (Block 0 (000800-001FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR1 = OFF // Table Read Protection Block 1 (Block 1 (002000-003FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR2 = OFF // Table Read Protection Block 2 (Block 2 (004000-005FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR3 = OFF // Table Read Protection Block 3 (Block 3 (006000-007FFFh) not protected from table reads executed in other blocks)
// CONFIG7H
#pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks)
#define _XTAL_FREQ 1000000
unsigned char myvar = 0x00;
unsigned char urx = 0x00;
void interrupt isr(void)
{
if(PIR1bits.RC1IF == 1)
{
urx = RCREG1;
LATD = urx;
PIR1bits.RC1IF = 0 ;
}
if(INTCONbits.T0IF == 1)
{
INTCONbits.TMR0IF = 0;
// toggle LED
LATBbits.LATB0 = ~LATBbits.LATB0;
myvar +=1;
TXREG1 = myvar;
}
if(PIR1bits.TMR1IF == 1)
{
PIR1bits.TMR1IF = 0;
// toggle LED
LATBbits.LATB1 = ~LATBbits.LATB1;
}
if(PIR1bits.TMR2IF == 1)
{
PIR1bits.TMR2IF = 0;
// toggle LED
LATBbits.LATB2 = ~LATBbits.LATB2;
}
}
void main(void) {
//*** Initialisation
// configure port
LATA = 0; // start with all output pins low (LED off)
TRISA = 0; // configure RA1 (only) as an output
TRISB = 0;
TRISCbits.TRISC6 = 0;
TRISCbits.TRISC7 = 1;
TRISD = 0;
// configure oscillator
//OSCCONbits.SCS1 = 1; // select internal clock
// OSCCONbits.IRCF = 0b0111; // internal oscillator = 500 kHz
OSCCON = 0b00110110;
//Timer0 configuration, 1MHZ
T0CON = 0b10000001;
INTCONbits.TMR0IE = 1;
//Timer1 Configuration
T1CON = 0b00000001;
PIE1bits.TMR1IE = 1;
//Timero2 Configuration
T2CON = 0b00010110;
PIE1bits.TMR2IE = 1;
//UART Configuration
//TX
SPBRG1 = 51; //300bps
TXSTA1bits.BRGH = 0;
BAUDCON1bits.BRG16 = 0;
TXSTA1bits.SYNC = 0; //Asyncronous
RCSTA1bits.SPEN = 1;
TXSTA1bits.TXEN = 1;
PIE1bits.TX1IE = 0;
//RX
PIE1bits.RC1IE = 1;
RCSTA1bits.CREN = 1;
//General interrupts
RCONbits.IPEN = 0;
INTCONbits.GIE = 1;
INTCONbits.PEIE = 1;
LATD = 0x00;
for (;;)
{
LATBbits.LATB4 = ~LATBbits.LATB4;
LATBbits.LATB3 = ~LATBbits.LATB3;
asm("NOP");
asm("NOP");
asm("NOP");
//__delay_ms(500);
} // repeat forever
}
INTCONbits.PEIE = 1;
//When IPEN = 0:
//1 = Enables all unmasked peripheral interrupts
//0 = Disables all peripheral interrupts
PIE1bits.RCIE = 1;
//1 = Enables the EUSART receive interrupt
//0 = Disables the EUSART receive interrupt
INTCONbits.GIE = 1;
//When IPEN = 0:
//1 = Enables all unmasked interrupts
//0 = Disables all interrupts including peripherals if(PIE1bits.RCIE && PIR1bits.RCIF){ // Did USART cause interrupt ?
/* EUSART Receive Interrupt Flag bit
RCIF: USART Receive Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
*/
if(RCSTAbits.OERR){
//OERR: Overrun Error bit
//1 = Overrun error (can be cleared by clearing bit CREN)
//0 = No overrun error
rcByte = RCREG; // clear the receiver fifo
rcByte = RCREG;
RCSTAbits.CREN = 0; // clear the OVR flag
RCSTAbits.CREN = 1;
// send (prepare) error message
return;
}// OVERRUN ERROR CLEARING
if(RCSTAbits.FERR){
//FERR: Framing Error bit
//1 = Framing error (can be updated by reading RCREG register and receive next valid byte)
//0 = No framing error
rcByte = RCREG;//ReadUSART(); // remove the broken byte
// send (prepare) error message
return;
}// FRAMING ERROR CLEARING
rcByte = RCREG; // ReadUSART();
}// RX Serial interrupt