; core_pins.h
#define CORE_PIN0_BIT 16
#define CORE_PIN1_BIT 17
#define CORE_PIN2_BIT 0
#define CORE_PIN3_BIT 12
#define CORE_PIN4_BIT 13
#define CORE_PIN5_BIT 7
#define CORE_PIN6_BIT 4
#define CORE_PIN7_BIT 2
#define CORE_PIN8_BIT 3
#define CORE_PIN9_BIT 3
#define CORE_PIN10_BIT 4
#define CORE_PIN11_BIT 6
#define CORE_PIN12_BIT 7
#define CORE_PIN13_BIT 5
#define CORE_PIN14_BIT 1
#define CORE_PIN15_BIT 0
#define CORE_PIN16_BIT 0
#define CORE_PIN17_BIT 1
#define CORE_PIN18_BIT 3
#define CORE_PIN19_BIT 2
#define CORE_PIN20_BIT 5
#define CORE_PIN21_BIT 6
#define CORE_PIN22_BIT 1
#define CORE_PIN23_BIT 2
#define CORE_PIN24_BIT 26
#define CORE_PIN25_BIT 5
#define CORE_PIN26_BIT 14
#define CORE_PIN27_BIT 15
#define CORE_PIN28_BIT 16
#define CORE_PIN29_BIT 18
#define CORE_PIN30_BIT 19
#define CORE_PIN31_BIT 10
#define CORE_PIN32_BIT 11
#define CORE_PIN33_BIT 24
#define CORE_PIN34_BIT 25
#define CORE_PIN35_BIT 8
#define CORE_PIN36_BIT 9
#define CORE_PIN37_BIT 10
#define CORE_PIN38_BIT 11
#define CORE_PIN39_BIT 17
#define CORE_PIN40_BIT 28
#define CORE_PIN41_BIT 29
#define CORE_PIN42_BIT 26
#define CORE_PIN43_BIT 20
#define CORE_PIN44_BIT 22
#define CORE_PIN45_BIT 23
#define CORE_PIN46_BIT 21
#define CORE_PIN47_BIT 8
#define CORE_PIN48_BIT 9
#define CORE_PIN49_BIT 4
#define CORE_PIN50_BIT 5
#define CORE_PIN51_BIT 14
#define CORE_PIN52_BIT 13
#define CORE_PIN53_BIT 12
#define CORE_PIN54_BIT 15
#define CORE_PIN55_BIT 11
#define CORE_PIN56_BIT 10
#define CORE_PIN57_BIT 11
#define CORE_PIN58_BIT 0
#define CORE_PIN59_BIT 1
#define CORE_PIN60_BIT 2
#define CORE_PIN61_BIT 3
#define CORE_PIN62_BIT 4
#define CORE_PIN63_BIT 5
#define CORE_PIN0_BITMASK (1<<(CORE_PIN0_BIT))
#define CORE_PIN1_BITMASK (1<<(CORE_PIN1_BIT))
#define CORE_PIN2_BITMASK (1<<(CORE_PIN2_BIT))
#define CORE_PIN3_BITMASK (1<<(CORE_PIN3_BIT))
#define CORE_PIN4_BITMASK (1<<(CORE_PIN4_BIT))
#define CORE_PIN5_BITMASK (1<<(CORE_PIN5_BIT))
#define CORE_PIN6_BITMASK (1<<(CORE_PIN6_BIT))
#define CORE_PIN7_BITMASK (1<<(CORE_PIN7_BIT))
#define CORE_PIN8_BITMASK (1<<(CORE_PIN8_BIT))
#define CORE_PIN9_BITMASK (1<<(CORE_PIN9_BIT))
#define CORE_PIN10_BITMASK (1<<(CORE_PIN10_BIT))
#define CORE_PIN11_BITMASK (1<<(CORE_PIN11_BIT))
#define CORE_PIN12_BITMASK (1<<(CORE_PIN12_BIT))
#define CORE_PIN13_BITMASK (1<<(CORE_PIN13_BIT))
#define CORE_PIN14_BITMASK (1<<(CORE_PIN14_BIT))
#define CORE_PIN15_BITMASK (1<<(CORE_PIN15_BIT))
#define CORE_PIN16_BITMASK (1<<(CORE_PIN16_BIT))
#define CORE_PIN17_BITMASK (1<<(CORE_PIN17_BIT))
#define CORE_PIN18_BITMASK (1<<(CORE_PIN18_BIT))
#define CORE_PIN19_BITMASK (1<<(CORE_PIN19_BIT))
#define CORE_PIN20_BITMASK (1<<(CORE_PIN20_BIT))
#define CORE_PIN21_BITMASK (1<<(CORE_PIN21_BIT))
#define CORE_PIN22_BITMASK (1<<(CORE_PIN22_BIT))
#define CORE_PIN23_BITMASK (1<<(CORE_PIN23_BIT))
#define CORE_PIN24_BITMASK (1<<(CORE_PIN24_BIT))
#define CORE_PIN25_BITMASK (1<<(CORE_PIN25_BIT))
#define CORE_PIN26_BITMASK (1<<(CORE_PIN26_BIT))
#define CORE_PIN27_BITMASK (1<<(CORE_PIN27_BIT))
#define CORE_PIN28_BITMASK (1<<(CORE_PIN28_BIT))
#define CORE_PIN29_BITMASK (1<<(CORE_PIN29_BIT))
#define CORE_PIN30_BITMASK (1<<(CORE_PIN30_BIT))
#define CORE_PIN31_BITMASK (1<<(CORE_PIN31_BIT))
#define CORE_PIN32_BITMASK (1<<(CORE_PIN32_BIT))
#define CORE_PIN33_BITMASK (1<<(CORE_PIN33_BIT))
#define CORE_PIN34_BITMASK (1<<(CORE_PIN34_BIT))
#define CORE_PIN35_BITMASK (1<<(CORE_PIN35_BIT))
#define CORE_PIN36_BITMASK (1<<(CORE_PIN36_BIT))
#define CORE_PIN37_BITMASK (1<<(CORE_PIN37_BIT))
#define CORE_PIN38_BITMASK (1<<(CORE_PIN38_BIT))
#define CORE_PIN39_BITMASK (1<<(CORE_PIN39_BIT))
#define CORE_PIN40_BITMASK (1<<(CORE_PIN40_BIT))
#define CORE_PIN41_BITMASK (1<<(CORE_PIN41_BIT))
#define CORE_PIN42_BITMASK (1<<(CORE_PIN42_BIT))
#define CORE_PIN43_BITMASK (1<<(CORE_PIN43_BIT))
#define CORE_PIN44_BITMASK (1<<(CORE_PIN44_BIT))
#define CORE_PIN45_BITMASK (1<<(CORE_PIN45_BIT))
#define CORE_PIN46_BITMASK (1<<(CORE_PIN46_BIT))
#define CORE_PIN47_BITMASK (1<<(CORE_PIN47_BIT))
#define CORE_PIN48_BITMASK (1<<(CORE_PIN48_BIT))
#define CORE_PIN49_BITMASK (1<<(CORE_PIN49_BIT))
#define CORE_PIN50_BITMASK (1<<(CORE_PIN50_BIT))
#define CORE_PIN51_BITMASK (1<<(CORE_PIN51_BIT))
#define CORE_PIN52_BITMASK (1<<(CORE_PIN52_BIT))
#define CORE_PIN53_BITMASK (1<<(CORE_PIN53_BIT))
#define CORE_PIN54_BITMASK (1<<(CORE_PIN54_BIT))
#define CORE_PIN55_BITMASK (1<<(CORE_PIN55_BIT))
#define CORE_PIN56_BITMASK (1<<(CORE_PIN56_BIT))
#define CORE_PIN57_BITMASK (1<<(CORE_PIN57_BIT))
#define CORE_PIN58_BITMASK (1<<(CORE_PIN58_BIT))
#define CORE_PIN59_BITMASK (1<<(CORE_PIN59_BIT))
#define CORE_PIN60_BITMASK (1<<(CORE_PIN60_BIT))
#define CORE_PIN61_BITMASK (1<<(CORE_PIN61_BIT))
#define CORE_PIN62_BITMASK (1<<(CORE_PIN62_BIT))
#define CORE_PIN63_BITMASK (1<<(CORE_PIN63_BIT))
#define CORE_PIN0_PORTREG GPIOB_PDOR
#define CORE_PIN1_PORTREG GPIOB_PDOR
#define CORE_PIN2_PORTREG GPIOD_PDOR
#define CORE_PIN3_PORTREG GPIOA_PDOR
#define CORE_PIN4_PORTREG GPIOA_PDOR
#define CORE_PIN5_PORTREG GPIOD_PDOR
#define CORE_PIN6_PORTREG GPIOD_PDOR
#define CORE_PIN7_PORTREG GPIOD_PDOR
#define CORE_PIN8_PORTREG GPIOD_PDOR
#define CORE_PIN9_PORTREG GPIOC_PDOR
#define CORE_PIN10_PORTREG GPIOC_PDOR
#define CORE_PIN11_PORTREG GPIOC_PDOR
#define CORE_PIN12_PORTREG GPIOC_PDOR
#define CORE_PIN13_PORTREG GPIOC_PDOR
#define CORE_PIN14_PORTREG GPIOD_PDOR
#define CORE_PIN15_PORTREG GPIOC_PDOR
#define CORE_PIN16_PORTREG GPIOB_PDOR
#define CORE_PIN17_PORTREG GPIOB_PDOR
#define CORE_PIN18_PORTREG GPIOB_PDOR
#define CORE_PIN19_PORTREG GPIOB_PDOR
#define CORE_PIN20_PORTREG GPIOD_PDOR
#define CORE_PIN21_PORTREG GPIOD_PDOR
#define CORE_PIN22_PORTREG GPIOC_PDOR
#define CORE_PIN23_PORTREG GPIOC_PDOR
#define CORE_PIN24_PORTREG GPIOE_PDOR
#define CORE_PIN25_PORTREG GPIOA_PDOR
#define CORE_PIN26_PORTREG GPIOA_PDOR
#define CORE_PIN27_PORTREG GPIOA_PDOR
#define CORE_PIN28_PORTREG GPIOA_PDOR
#define CORE_PIN29_PORTREG GPIOB_PDOR
#define CORE_PIN30_PORTREG GPIOB_PDOR
#define CORE_PIN31_PORTREG GPIOB_PDOR
#define CORE_PIN32_PORTREG GPIOB_PDOR
#define CORE_PIN33_PORTREG GPIOE_PDOR
#define CORE_PIN34_PORTREG GPIOE_PDOR
#define CORE_PIN35_PORTREG GPIOC_PDOR
#define CORE_PIN36_PORTREG GPIOC_PDOR
#define CORE_PIN37_PORTREG GPIOC_PDOR
#define CORE_PIN38_PORTREG GPIOC_PDOR
#define CORE_PIN39_PORTREG GPIOA_PDOR
#define CORE_PIN40_PORTREG GPIOA_PDOR
#define CORE_PIN41_PORTREG GPIOA_PDOR
#define CORE_PIN42_PORTREG GPIOA_PDOR
#define CORE_PIN43_PORTREG GPIOB_PDOR
#define CORE_PIN44_PORTREG GPIOB_PDOR
#define CORE_PIN45_PORTREG GPIOB_PDOR
#define CORE_PIN46_PORTREG GPIOB_PDOR
#define CORE_PIN47_PORTREG GPIOD_PDOR
#define CORE_PIN48_PORTREG GPIOD_PDOR
#define CORE_PIN49_PORTREG GPIOB_PDOR
#define CORE_PIN50_PORTREG GPIOB_PDOR
#define CORE_PIN51_PORTREG GPIOD_PDOR
#define CORE_PIN52_PORTREG GPIOD_PDOR
#define CORE_PIN53_PORTREG GPIOD_PDOR
#define CORE_PIN54_PORTREG GPIOD_PDOR
#define CORE_PIN55_PORTREG GPIOD_PDOR
#define CORE_PIN56_PORTREG GPIOE_PDOR
#define CORE_PIN57_PORTREG GPIOE_PDOR
#define CORE_PIN58_PORTREG GPIOE_PDOR
#define CORE_PIN59_PORTREG GPIOE_PDOR
#define CORE_PIN60_PORTREG GPIOE_PDOR
#define CORE_PIN61_PORTREG GPIOE_PDOR
#define CORE_PIN62_PORTREG GPIOE_PDOR
#define CORE_PIN63_PORTREG GPIOE_PDOR
#define CORE_PIN0_PORTSET GPIOB_PSOR
#define CORE_PIN1_PORTSET GPIOB_PSOR
#define CORE_PIN2_PORTSET GPIOD_PSOR
#define CORE_PIN3_PORTSET GPIOA_PSOR
#define CORE_PIN4_PORTSET GPIOA_PSOR
#define CORE_PIN5_PORTSET GPIOD_PSOR
#define CORE_PIN6_PORTSET GPIOD_PSOR
#define CORE_PIN7_PORTSET GPIOD_PSOR
#define CORE_PIN8_PORTSET GPIOD_PSOR
#define CORE_PIN9_PORTSET GPIOC_PSOR
#define CORE_PIN10_PORTSET GPIOC_PSOR
#define CORE_PIN11_PORTSET GPIOC_PSOR
#define CORE_PIN12_PORTSET GPIOC_PSOR
#define CORE_PIN13_PORTSET GPIOC_PSOR
#define CORE_PIN14_PORTSET GPIOD_PSOR
#define CORE_PIN15_PORTSET GPIOC_PSOR
#define CORE_PIN16_PORTSET GPIOB_PSOR
#define CORE_PIN17_PORTSET GPIOB_PSOR
#define CORE_PIN18_PORTSET GPIOB_PSOR
#define CORE_PIN19_PORTSET GPIOB_PSOR
#define CORE_PIN20_PORTSET GPIOD_PSOR
#define CORE_PIN21_PORTSET GPIOD_PSOR
#define CORE_PIN22_PORTSET GPIOC_PSOR
#define CORE_PIN23_PORTSET GPIOC_PSOR
#define CORE_PIN24_PORTSET GPIOE_PSOR
#define CORE_PIN25_PORTSET GPIOA_PSOR
#define CORE_PIN26_PORTSET GPIOA_PSOR
#define CORE_PIN27_PORTSET GPIOA_PSOR
#define CORE_PIN28_PORTSET GPIOA_PSOR
#define CORE_PIN29_PORTSET GPIOB_PSOR
#define CORE_PIN30_PORTSET GPIOB_PSOR
#define CORE_PIN31_PORTSET GPIOB_PSOR
#define CORE_PIN32_PORTSET GPIOB_PSOR
#define CORE_PIN33_PORTSET GPIOE_PSOR
#define CORE_PIN34_PORTSET GPIOE_PSOR
#define CORE_PIN35_PORTSET GPIOC_PSOR
#define CORE_PIN36_PORTSET GPIOC_PSOR
#define CORE_PIN37_PORTSET GPIOC_PSOR
#define CORE_PIN38_PORTSET GPIOC_PSOR
#define CORE_PIN39_PORTSET GPIOA_PSOR
#define CORE_PIN40_PORTSET GPIOA_PSOR
#define CORE_PIN41_PORTSET GPIOA_PSOR
#define CORE_PIN42_PORTSET GPIOA_PSOR
#define CORE_PIN43_PORTSET GPIOB_PSOR
#define CORE_PIN44_PORTSET GPIOB_PSOR
#define CORE_PIN45_PORTSET GPIOB_PSOR
#define CORE_PIN46_PORTSET GPIOB_PSOR
#define CORE_PIN47_PORTSET GPIOD_PSOR
#define CORE_PIN48_PORTSET GPIOD_PSOR
#define CORE_PIN49_PORTSET GPIOB_PSOR
#define CORE_PIN50_PORTSET GPIOB_PSOR
#define CORE_PIN51_PORTSET GPIOD_PSOR
#define CORE_PIN52_PORTSET GPIOD_PSOR
#define CORE_PIN53_PORTSET GPIOD_PSOR
#define CORE_PIN54_PORTSET GPIOD_PSOR
#define CORE_PIN55_PORTSET GPIOD_PSOR
#define CORE_PIN56_PORTSET GPIOE_PSOR
#define CORE_PIN57_PORTSET GPIOE_PSOR
#define CORE_PIN58_PORTSET GPIOE_PSOR
#define CORE_PIN59_PORTSET GPIOE_PSOR
#define CORE_PIN60_PORTSET GPIOE_PSOR
#define CORE_PIN61_PORTSET GPIOE_PSOR
#define CORE_PIN62_PORTSET GPIOE_PSOR
#define CORE_PIN63_PORTSET GPIOE_PSOR
#define CORE_PIN0_PORTCLEAR GPIOB_PCOR
#define CORE_PIN1_PORTCLEAR GPIOB_PCOR
#define CORE_PIN2_PORTCLEAR GPIOD_PCOR
#define CORE_PIN3_PORTCLEAR GPIOA_PCOR
#define CORE_PIN4_PORTCLEAR GPIOA_PCOR
#define CORE_PIN5_PORTCLEAR GPIOD_PCOR
#define CORE_PIN6_PORTCLEAR GPIOD_PCOR
#define CORE_PIN7_PORTCLEAR GPIOD_PCOR
#define CORE_PIN8_PORTCLEAR GPIOD_PCOR
#define CORE_PIN9_PORTCLEAR GPIOC_PCOR
#define CORE_PIN10_PORTCLEAR GPIOC_PCOR
#define CORE_PIN11_PORTCLEAR GPIOC_PCOR
#define CORE_PIN12_PORTCLEAR GPIOC_PCOR
#define CORE_PIN13_PORTCLEAR GPIOC_PCOR
#define CORE_PIN14_PORTCLEAR GPIOD_PCOR
#define CORE_PIN15_PORTCLEAR GPIOC_PCOR
#define CORE_PIN16_PORTCLEAR GPIOB_PCOR
#define CORE_PIN17_PORTCLEAR GPIOB_PCOR
#define CORE_PIN18_PORTCLEAR GPIOB_PCOR
#define CORE_PIN19_PORTCLEAR GPIOB_PCOR
#define CORE_PIN20_PORTCLEAR GPIOD_PCOR
#define CORE_PIN21_PORTCLEAR GPIOD_PCOR
#define CORE_PIN22_PORTCLEAR GPIOC_PCOR
#define CORE_PIN23_PORTCLEAR GPIOC_PCOR
#define CORE_PIN24_PORTCLEAR GPIOE_PCOR
#define CORE_PIN25_PORTCLEAR GPIOA_PCOR
#define CORE_PIN26_PORTCLEAR GPIOA_PCOR
#define CORE_PIN27_PORTCLEAR GPIOA_PCOR
#define CORE_PIN28_PORTCLEAR GPIOA_PCOR
#define CORE_PIN29_PORTCLEAR GPIOB_PCOR
#define CORE_PIN30_PORTCLEAR GPIOB_PCOR
#define CORE_PIN31_PORTCLEAR GPIOB_PCOR
#define CORE_PIN32_PORTCLEAR GPIOB_PCOR
#define CORE_PIN33_PORTCLEAR GPIOE_PCOR
#define CORE_PIN34_PORTCLEAR GPIOE_PCOR
#define CORE_PIN35_PORTCLEAR GPIOC_PCOR
#define CORE_PIN36_PORTCLEAR GPIOC_PCOR
#define CORE_PIN37_PORTCLEAR GPIOC_PCOR
#define CORE_PIN38_PORTCLEAR GPIOC_PCOR
#define CORE_PIN39_PORTCLEAR GPIOA_PCOR
#define CORE_PIN40_PORTCLEAR GPIOA_PCOR
#define CORE_PIN41_PORTCLEAR GPIOA_PCOR
#define CORE_PIN42_PORTCLEAR GPIOA_PCOR
#define CORE_PIN43_PORTCLEAR GPIOB_PCOR
#define CORE_PIN44_PORTCLEAR GPIOB_PCOR
#define CORE_PIN45_PORTCLEAR GPIOB_PCOR
#define CORE_PIN46_PORTCLEAR GPIOB_PCOR
#define CORE_PIN47_PORTCLEAR GPIOD_PCOR
#define CORE_PIN48_PORTCLEAR GPIOD_PCOR
#define CORE_PIN49_PORTCLEAR GPIOB_PCOR
#define CORE_PIN50_PORTCLEAR GPIOB_PCOR
#define CORE_PIN51_PORTCLEAR GPIOD_PCOR
#define CORE_PIN52_PORTCLEAR GPIOD_PCOR
#define CORE_PIN53_PORTCLEAR GPIOD_PCOR
#define CORE_PIN54_PORTCLEAR GPIOD_PCOR
#define CORE_PIN55_PORTCLEAR GPIOD_PCOR
#define CORE_PIN56_PORTCLEAR GPIOE_PCOR
#define CORE_PIN57_PORTCLEAR GPIOE_PCOR
#define CORE_PIN58_PORTCLEAR GPIOE_PCOR
#define CORE_PIN59_PORTCLEAR GPIOE_PCOR
#define CORE_PIN60_PORTCLEAR GPIOE_PCOR
#define CORE_PIN61_PORTCLEAR GPIOE_PCOR
#define CORE_PIN62_PORTCLEAR GPIOE_PCOR
#define CORE_PIN63_PORTCLEAR GPIOE_PCOR
#define CORE_PIN0_DDRREG GPIOB_PDDR
#define CORE_PIN1_DDRREG GPIOB_PDDR
#define CORE_PIN2_DDRREG GPIOD_PDDR
#define CORE_PIN3_DDRREG GPIOA_PDDR
#define CORE_PIN4_DDRREG GPIOA_PDDR
#define CORE_PIN5_DDRREG GPIOD_PDDR
#define CORE_PIN6_DDRREG GPIOD_PDDR
#define CORE_PIN7_DDRREG GPIOD_PDDR
#define CORE_PIN8_DDRREG GPIOD_PDDR
#define CORE_PIN9_DDRREG GPIOC_PDDR
#define CORE_PIN10_DDRREG GPIOC_PDDR
#define CORE_PIN11_DDRREG GPIOC_PDDR
#define CORE_PIN12_DDRREG GPIOC_PDDR
#define CORE_PIN13_DDRREG GPIOC_PDDR
#define CORE_PIN14_DDRREG GPIOD_PDDR
#define CORE_PIN15_DDRREG GPIOC_PDDR
#define CORE_PIN16_DDRREG GPIOB_PDDR
#define CORE_PIN17_DDRREG GPIOB_PDDR
#define CORE_PIN18_DDRREG GPIOB_PDDR
#define CORE_PIN19_DDRREG GPIOB_PDDR
#define CORE_PIN20_DDRREG GPIOD_PDDR
#define CORE_PIN21_DDRREG GPIOD_PDDR
#define CORE_PIN22_DDRREG GPIOC_PDDR
#define CORE_PIN23_DDRREG GPIOC_PDDR
#define CORE_PIN24_DDRREG GPIOE_PDDR
#define CORE_PIN25_DDRREG GPIOA_PDDR
#define CORE_PIN26_DDRREG GPIOA_PDDR
#define CORE_PIN27_DDRREG GPIOA_PDDR
#define CORE_PIN28_DDRREG GPIOA_PDDR
#define CORE_PIN29_DDRREG GPIOB_PDDR
#define CORE_PIN30_DDRREG GPIOB_PDDR
#define CORE_PIN31_DDRREG GPIOB_PDDR
#define CORE_PIN32_DDRREG GPIOB_PDDR
#define CORE_PIN33_DDRREG GPIOE_PDDR
#define CORE_PIN34_DDRREG GPIOE_PDDR
#define CORE_PIN35_DDRREG GPIOC_PDDR
#define CORE_PIN36_DDRREG GPIOC_PDDR
#define CORE_PIN37_DDRREG GPIOC_PDDR
#define CORE_PIN38_DDRREG GPIOC_PDDR
#define CORE_PIN39_DDRREG GPIOA_PDDR
#define CORE_PIN40_DDRREG GPIOA_PDDR
#define CORE_PIN41_DDRREG GPIOA_PDDR
#define CORE_PIN42_DDRREG GPIOA_PDDR
#define CORE_PIN43_DDRREG GPIOB_PDDR
#define CORE_PIN44_DDRREG GPIOB_PDDR
#define CORE_PIN45_DDRREG GPIOB_PDDR
#define CORE_PIN46_DDRREG GPIOB_PDDR
#define CORE_PIN47_DDRREG GPIOD_PDDR
#define CORE_PIN48_DDRREG GPIOD_PDDR
#define CORE_PIN49_DDRREG GPIOB_PDDR
#define CORE_PIN50_DDRREG GPIOB_PDDR
#define CORE_PIN51_DDRREG GPIOD_PDDR
#define CORE_PIN52_DDRREG GPIOD_PDDR
#define CORE_PIN53_DDRREG GPIOD_PDDR
#define CORE_PIN54_DDRREG GPIOD_PDDR
#define CORE_PIN55_DDRREG GPIOD_PDDR
#define CORE_PIN56_DDRREG GPIOE_PDDR
#define CORE_PIN57_DDRREG GPIOE_PDDR
#define CORE_PIN58_DDRREG GPIOE_PDDR
#define CORE_PIN59_DDRREG GPIOE_PDDR
#define CORE_PIN60_DDRREG GPIOE_PDDR
#define CORE_PIN61_DDRREG GPIOE_PDDR
#define CORE_PIN62_DDRREG GPIOE_PDDR
#define CORE_PIN63_DDRREG GPIOE_PDDR
#define CORE_PIN0_PINREG GPIOB_PDIR
#define CORE_PIN1_PINREG GPIOB_PDIR
#define CORE_PIN2_PINREG GPIOD_PDIR
#define CORE_PIN3_PINREG GPIOA_PDIR
#define CORE_PIN4_PINREG GPIOA_PDIR
#define CORE_PIN5_PINREG GPIOD_PDIR
#define CORE_PIN6_PINREG GPIOD_PDIR
#define CORE_PIN7_PINREG GPIOD_PDIR
#define CORE_PIN8_PINREG GPIOD_PDIR
#define CORE_PIN9_PINREG GPIOC_PDIR
#define CORE_PIN10_PINREG GPIOC_PDIR
#define CORE_PIN11_PINREG GPIOC_PDIR
#define CORE_PIN12_PINREG GPIOC_PDIR
#define CORE_PIN13_PINREG GPIOC_PDIR
#define CORE_PIN14_PINREG GPIOD_PDIR
#define CORE_PIN15_PINREG GPIOC_PDIR
#define CORE_PIN16_PINREG GPIOB_PDIR
#define CORE_PIN17_PINREG GPIOB_PDIR
#define CORE_PIN18_PINREG GPIOB_PDIR
#define CORE_PIN19_PINREG GPIOB_PDIR
#define CORE_PIN20_PINREG GPIOD_PDIR
#define CORE_PIN21_PINREG GPIOD_PDIR
#define CORE_PIN22_PINREG GPIOC_PDIR
#define CORE_PIN23_PINREG GPIOC_PDIR
#define CORE_PIN24_PINREG GPIOE_PDIR
#define CORE_PIN25_PINREG GPIOA_PDIR
#define CORE_PIN26_PINREG GPIOA_PDIR
#define CORE_PIN27_PINREG GPIOA_PDIR
#define CORE_PIN28_PINREG GPIOA_PDIR
#define CORE_PIN29_PINREG GPIOB_PDIR
#define CORE_PIN30_PINREG GPIOB_PDIR
#define CORE_PIN31_PINREG GPIOB_PDIR
#define CORE_PIN32_PINREG GPIOB_PDIR
#define CORE_PIN33_PINREG GPIOE_PDIR
#define CORE_PIN34_PINREG GPIOE_PDIR
#define CORE_PIN35_PINREG GPIOC_PDIR
#define CORE_PIN36_PINREG GPIOC_PDIR
#define CORE_PIN37_PINREG GPIOC_PDIR
#define CORE_PIN38_PINREG GPIOC_PDIR
#define CORE_PIN39_PINREG GPIOA_PDIR
#define CORE_PIN40_PINREG GPIOA_PDIR
#define CORE_PIN41_PINREG GPIOA_PDIR
#define CORE_PIN42_PINREG GPIOA_PDIR
#define CORE_PIN43_PINREG GPIOB_PDIR
#define CORE_PIN44_PINREG GPIOB_PDIR
#define CORE_PIN45_PINREG GPIOB_PDIR
#define CORE_PIN46_PINREG GPIOB_PDIR
#define CORE_PIN47_PINREG GPIOD_PDIR
#define CORE_PIN48_PINREG GPIOD_PDIR
#define CORE_PIN49_PINREG GPIOB_PDIR
#define CORE_PIN50_PINREG GPIOB_PDIR
#define CORE_PIN51_PINREG GPIOD_PDIR
#define CORE_PIN52_PINREG GPIOD_PDIR
#define CORE_PIN53_PINREG GPIOD_PDIR
#define CORE_PIN54_PINREG GPIOD_PDIR
#define CORE_PIN55_PINREG GPIOD_PDIR
#define CORE_PIN56_PINREG GPIOE_PDIR
#define CORE_PIN57_PINREG GPIOE_PDIR
#define CORE_PIN58_PINREG GPIOE_PDIR
#define CORE_PIN59_PINREG GPIOE_PDIR
#define CORE_PIN60_PINREG GPIOE_PDIR
#define CORE_PIN61_PINREG GPIOE_PDIR
#define CORE_PIN62_PINREG GPIOE_PDIR
#define CORE_PIN63_PINREG GPIOE_PDIR
#define CORE_PIN0_CONFIG PORTB_PCR16
#define CORE_PIN1_CONFIG PORTB_PCR17
#define CORE_PIN2_CONFIG PORTD_PCR0
#define CORE_PIN3_CONFIG PORTA_PCR12
#define CORE_PIN4_CONFIG PORTA_PCR13
#define CORE_PIN5_CONFIG PORTD_PCR7
#define CORE_PIN6_CONFIG PORTD_PCR4
#define CORE_PIN7_CONFIG PORTD_PCR2
#define CORE_PIN8_CONFIG PORTD_PCR3
#define CORE_PIN9_CONFIG PORTC_PCR3
#define CORE_PIN10_CONFIG PORTC_PCR4
#define CORE_PIN11_CONFIG PORTC_PCR6
#define CORE_PIN12_CONFIG PORTC_PCR7
#define CORE_PIN13_CONFIG PORTC_PCR5
#define CORE_PIN14_CONFIG PORTD_PCR1
#define CORE_PIN15_CONFIG PORTC_PCR0
#define CORE_PIN16_CONFIG PORTB_PCR0
#define CORE_PIN17_CONFIG PORTB_PCR1
#define CORE_PIN18_CONFIG PORTB_PCR3
#define CORE_PIN19_CONFIG PORTB_PCR2
#define CORE_PIN20_CONFIG PORTD_PCR5
#define CORE_PIN21_CONFIG PORTD_PCR6
#define CORE_PIN22_CONFIG PORTC_PCR1
#define CORE_PIN23_CONFIG PORTC_PCR2
#define CORE_PIN24_CONFIG PORTE_PCR26
#define CORE_PIN25_CONFIG PORTA_PCR5
#define CORE_PIN26_CONFIG PORTA_PCR14
#define CORE_PIN27_CONFIG PORTA_PCR15
#define CORE_PIN28_CONFIG PORTA_PCR16
#define CORE_PIN29_CONFIG PORTB_PCR18
#define CORE_PIN30_CONFIG PORTB_PCR19
#define CORE_PIN31_CONFIG PORTB_PCR10
#define CORE_PIN32_CONFIG PORTB_PCR11
#define CORE_PIN33_CONFIG PORTE_PCR24
#define CORE_PIN34_CONFIG PORTE_PCR25
#define CORE_PIN35_CONFIG PORTC_PCR8
#define CORE_PIN36_CONFIG PORTC_PCR9
#define CORE_PIN37_CONFIG PORTC_PCR10
#define CORE_PIN38_CONFIG PORTC_PCR11
#define CORE_PIN39_CONFIG PORTA_PCR17
#define CORE_PIN40_CONFIG PORTA_PCR28
#define CORE_PIN41_CONFIG PORTA_PCR29
#define CORE_PIN42_CONFIG PORTA_PCR26
#define CORE_PIN43_CONFIG PORTB_PCR20
#define CORE_PIN44_CONFIG PORTB_PCR22
#define CORE_PIN45_CONFIG PORTB_PCR23
#define CORE_PIN46_CONFIG PORTB_PCR21
#define CORE_PIN47_CONFIG PORTD_PCR8
#define CORE_PIN48_CONFIG PORTD_PCR9
#define CORE_PIN49_CONFIG PORTB_PCR4
#define CORE_PIN50_CONFIG PORTB_PCR5
#define CORE_PIN51_CONFIG PORTD_PCR14
#define CORE_PIN52_CONFIG PORTD_PCR13
#define CORE_PIN53_CONFIG PORTD_PCR12
#define CORE_PIN54_CONFIG PORTD_PCR15
#define CORE_PIN55_CONFIG PORTD_PCR11
#define CORE_PIN56_CONFIG PORTE_PCR10
#define CORE_PIN57_CONFIG PORTE_PCR11
#define CORE_PIN58_CONFIG PORTE_PCR0
#define CORE_PIN59_CONFIG PORTE_PCR1
#define CORE_PIN60_CONFIG PORTE_PCR2
#define CORE_PIN61_CONFIG PORTE_PCR3
#define CORE_PIN62_CONFIG PORTE_PCR4
#define CORE_PIN63_CONFIG PORTE_PCR5