library ieee;
use ieee.std_logic_1164.all;
entity display_controller is
port(
d_in: in std_logic_vector(6 downto 0);
d_out: out std_logic_vector(6 downto 0);
clk : in std_logic;
address: in std_logic;
load: in std_logic;
clear: in std_logic;
reset: in std_logic;
mux_out: out std_logic_vector(1 downto 0)
);
end display_controller;
architecture behave of display_controller is
component register7 is
port(
d_in : in std_logic_vector(6 downto 0);
load : in std_logic;
clear: in std_logic;
clk : in std_logic;
d_out: out std_logic_vector(6 downto 0)
);
end component;
type state_type is (dig_0,dig_1);
signal State: state_type;
signal d_out_0: std_logic_vector(6 downto 0);
signal d_out_1: std_logic_vector(6 downto 0);
signal load_0: std_logic;
signal load_1: std_logic;
signal clear_0: std_logic;
signal clear_1: std_logic;
begin
U0: register7
port map(
d_in => d_in,
load => load_0,
clear => clear_0,
clk => clk,
d_out => d_out_0
);
U1: register7
port map(
d_in => d_in,
load => load_1,
clear => clear_1,
clk => clk,
d_out => d_out_1
);
load_in: process(load, address)
begin
case address is
when '0' => load_0 <= load; load_1 <= '0';
when '1' => load_0 <= '0'; load_1 <= load;
when others => load_0 <= load; load_1 <= '0';
end case;
end process;
clear_in: process(clear, address)
begin
case address is
when '0' => clear_0 <= clear; clear_1<= '0';
when '1' => clear_0 <= '0'; clear_1 <= clear;
when others => clear_0 <= clear; clear_1<= '0';
end case;
end process;
dout_state: process(d_out_0, d_out_1, reset, clk)
begin
if(reset='1') then
State <= dig_0;
elsif rising_edge(clk) then
case State is
when dig_0 => d_out <= d_out_0; mux_out <= "01"; State <= dig_1;
when dig_1 => d_out <= d_out_1; mux_out <= "10"; State <= dig_0;
when others => d_out <= d_out_0; mux_out <= "01"; State <= dig_1;
end case;
end if;
end process;
end behave;