;****************************************************************************
; PIC16F87x Family Header
; Copyright 1995, 2002 microEngineering Labs, Inc.
;****************************************************************************
NOLIST
; *** Default Device Specifications
DEVICE 3FFF3FFFh ; All Fuse Bits On
DEVICE 50101004h ; 14-Bit, 8K Code, 256 EE, ID = 4
; *** DEVICE Device Definitions
PIC16F873 equ 50080803h ; 14-Bit, 4K Code, 128 EE, ID = 3
PIC16F874 equ 50080803h ; 14-Bit, 4K Code, 128 EE, ID = 3
PIC16F876 equ 50101004h ; 14-Bit, 8K Code, 256 EE, ID = 4
PIC16F877 equ 50101004h ; 14-Bit, 8K Code, 256 EE, ID = 4
; *** DEVICE Fuses Definitions
RC_OSC equ 3FFC0003h ; XX XXXX XXXX XX11
HS_OSC equ 3FFC0002h ; XX XXXX XXXX XX10
XT_OSC equ 3FFC0001h ; XX XXXX XXXX XX01
LP_OSC equ 3FFC0000h ; XX XXXX XXXX XX00
WDT_ON equ 3FFB0004h ; XX XXXX XXXX X1XX
WDT_OFF equ 3FFB0000h ; XX XXXX XXXX X0XX
PWRT_ON equ 3FF70000h ; XX XXXX XXXX 0XXX
PWRT_OFF equ 3FF70008h ; XX XXXX XXXX 1XXX
BOD_ON equ 3FBF0040h ; XX XXXX X1XX XXXX
BOD_OFF equ 3FBF0000h ; XX XXXX X0XX XXXX
LVP_ON equ 3F7F0080h ; XX XXXX 1XXX XXXX
LVP_OFF equ 3F7F0000h ; XX XXXX 0XXX XXXX
CPD_ON equ 3EFF0000h ; XX XXX0 XXXX XXXX
CPD_OFF equ 3EFF0100h ; XX XXX1 XXXX XXXX
WRT_ON equ 3DFF0200h ; XX XX1X XXXX XXXX
WRT_OFF equ 3DFF0000h ; XX XX0X XXXX XXXX
DEBUG_ON equ 37FF0000h ; XX 0XXX XXXX XXXX
DEBUG_OFF equ 37FF0800h ; XX 1XXX XXXX XXXX
PROTECT_ON equ 0FCF0000h ; 00 XXXX XX00 XXXX
PROTECT_OFF equ 0FCF3030h ; 11 XXXX XX11 XXXX
; *** Register Names
INDF equ 00h ; Indirect Data
TMR0 equ 01h ; Real Time Clock/Counter
PCL equ 02h ; Program Counter (LSB)
STATUS equ 03h ; Status Flags
FSR equ 04h ; File Select Register
PORTA equ 05h ; Port A Data
PORTB equ 06h ; Port B Data
PORTC equ 07h ; Port C Data
PORTD equ 08h ; Port D Data
PORTE equ 09h ; Port E Data
PCLATH equ 0Ah ; Program Counter (MSB)
INTCON equ 0Bh ; Interrupt Control
PIR1 equ 0Ch ; Peripheral Interrupt Flags 1
PIR2 equ 0Dh ; Peripheral Interrupt Flags 2
TMR1L equ 0Eh ; Timer 1 Data (LSB)
TMR1H equ 0Fh ; Timer 1 Data (MSB)
T1CON equ 10h ; Timer 1 Control
TMR2 equ 11h ; Timer 2 Data
T2CON equ 12h ; Timer 2 Control
SSPBUF equ 13h ; SSP Data
SSPCON equ 14h ; SSP Control
CCPR1L equ 15h ; CCP 1 Data (LSB)
CCPR1H equ 16h ; CCP 1 Data (MSB)
CCP1CON equ 17h ; CCP 1 Control
RCSTA equ 18h ; ASP Status/Control
TXREG equ 19h ; ASP Transmit Data
RCREG equ 1Ah ; ASP Receive Data
CCPR2L equ 1Bh ; CCP 2 Data (LSB)
CCPR2H equ 1Ch ; CCP 2 Data (MSB)
CCP2CON equ 1Dh ; CCP 2 Control
ADRESH equ 1Eh ; A/D Result High
ADRES equ 1Eh ; A/D Result High
ADCON0 equ 1Fh ; A/D Control 0
OPTION_REG equ 81h ; OPTION Register
TRISA equ 85h ; Port A Tristate Control
TRISB equ 86h ; Port B Tristate Control
TRISC equ 87h ; Port C Tristate Control
TRISD equ 88h ; Port D Tristate Control
TRISE equ 89h ; Port E Tristate Control
PIE1 equ 8Ch ; Peripheral Interrupt Enables 1
PIE2 equ 8Dh ; Peripheral Interrupt Enables 2
PCON equ 8Eh ; Power Control
SSPCON2 equ 91h ; SSP Control 2
PR2 equ 92h ; Timer 2 Period
SSPADD equ 93h ; SSP I2C Address
SSPSTAT equ 94h ; SSP Status Flags
TXSTA equ 98h ; ASP Transmit Status/Control
SPBRG equ 99h ; ASP Baud Rate
ADRESL equ 9Eh ; A/D Result Low
ADCON1 equ 9Fh ; A/D Control 1
EEDATA equ 10Ch ; EEPROM Data
EEADR equ 10Dh ; EEPROM Address
EEDATH equ 10Eh ; EEPROM Data High
EEADRH equ 10Fh ; EEPROM Address High
EECON1 equ 18Ch ; EEPROM Control 1
EECON2 equ 18Dh ; EEPROM Control 2
; *** STATUS Bits
C equ 0 ; Carry
DC equ 1 ; Digit (Half) Carry
Z equ 2 ; Zero
PD equ 3 ; Power Down
TO equ 4 ; Time Out
RP0 equ 5 ; Direct Data Page Select 0
RP1 equ 6 ; Direct Data Page Select 1
IRP equ 7 ; Indirect Data Page Select
; *** INTCON Bits
RBIF equ 0 ; PORTB[4..7] Change Interrupt Flag
INTF equ 1 ; RB0/INT Interrupt Flag
T0IF equ 2 ; TMR0 Overflow Interrupt Flag
RBIE equ 3 ; PORTB[4..7] Change Interrupt Enable
INTE equ 4 ; RB0/INT Interrupt Enable
T0IE equ 5 ; TMR0 Overflow Interrupt Enable
PEIE equ 6 ; Peripheral Interrupt Enable
GIE equ 7 ; Global Interrupt Enable
; *** PIR1 Bits
TMR1IF equ 0 ; Timer 1 Interrupt Flag
TMR2IF equ 1 ; Timer 2 Interrupt Flag
CCP1IF equ 2 ; CCP 1 Interrupt Flag
SSPIF equ 3 ; SSP Interrupt Flag
TXIF equ 4 ; ASP Transmit Interrupt Flag
RCIF equ 5 ; ASP Receive Interrupt Flag
ADIF equ 6 ; A/D Interrupt Flag
PSPIF equ 7 ; PSP Interrupt Flag
; *** PIR2 Bits
CCP2IF equ 0 ; CCP 2 Interrupt Flag
BCLIF equ 3 ; Bus Collision Interrupt Flag
EEIF equ 4 ; EEPROM Interrupt Flag
; *** T1CON Bits
TMR1ON equ 0 ; Timer 1 Enable
TMR1CS equ 1 ; Timer 1 Clock Select
T1INSYNC equ 2 ; Timer 1 Sync Enable
T1OSCEN equ 3 ; Timer 1 Oscillator Enable
T1CKPS0 equ 4 ; Timer 1 Prescaler Select (2 Bits)
T1CKPS1 equ 5
; *** T2CON Bits
T2CKPS0 equ 0 ; Timer 2 Prescaler Select (2 Bits)
T2CKPS1 equ 1
TMR2ON equ 2 ; Timer 2 Enable
TOUTPS0 equ 3 ; Timer 2 Postscaler Select (4 Bits)
TOUTPS1 equ 4
TOUTPS2 equ 5
TOUTPS3 equ 6
; *** SSPCON Bits
SSPM0 equ 0 ; SSP Mode Select (4 Bits)
SSPM1 equ 1
SSPM2 equ 2
SSPM3 equ 3
CKP equ 4 ; SSP Clock Polarity Select
SSPEN equ 5 ; SSP Enable
SSPOV equ 6 ; SSP Receive Overflow Flag
WCOL equ 7 ; SSP Write Collision Detect
; *** CCP1CON Bits
CCP1M0 equ 0 ; CCP 1 Mode Select (4 Bits)
CCP1M1 equ 1
CCP1M2 equ 2
CCP1M3 equ 3
CCP1Y equ 4 ; CCP 1 PWM Bit 0
CCP1X equ 5 ; CCP 1 PWM Bit 1
; *** RCSTA Bits
RX9D equ 0 ; ASP Received 9th/Parity Bit
OERR equ 1 ; ASP Overrun Flag
FERR equ 2 ; ASP Framing Error Flag
ADDEN equ 3
CREN equ 4 ; ASP Continuous Receive Enable
SREN equ 5 ; ASP Single Receive Enable
RX9 equ 6 ; ASP Receive Data Length Select
SPEN equ 7 ; ASP Enable
; *** CCP2CON Bits
CCP2M0 equ 0 ; CCP 2 Mode Select (4 Bits)
CCP2M1 equ 1
CCP2M2 equ 2
CCP2M3 equ 3
CCP2Y equ 4 ; CCP 2 PWM Bit 0
CCP2X equ 5 ; CCP 2 PWM Bit 1
; *** ADCON0 Bits
ADON equ 0 ; A/D Power Control
GO_DONE equ 2 ; A/D GO/DONE Bit
CHS0 equ 3 ; A/D Channel Select (4 Bits)
CHS1 equ 4
CHS2 equ 5
ADCS0 equ 6 ; A/D Clock Select (2 Bits)
ADCS1 equ 7
; *** OPTION Bits
PS0 equ 0 ; Prescaler Divisor Select (3 Bits)
PS1 equ 1
PS2 equ 2
PSA equ 3 ; Prescaler Assignment
T0SE equ 4 ; Timer 0 Source Edge Select
T0CS equ 5 ; Timer 0 Clock Source Select
INTEDG equ 6 ; RB0/INT Edge Select
RBPU equ 7 ; Port B Weak Pull-Up Enable
; *** TRISE Bits
TRISE0 equ 0 ; PORTE[0..2] Tristate Control (3 Bits)
TRISE1 equ 1
TRISE2 equ 2
PSPMODE equ 4 ; PSP Mode Select
IBOV equ 5 ; PSP Input Buffer Overflow Flag
OBF equ 6 ; PSP Output Buffer Full Flag
IBF equ 7 ; PSP input Buffer Full Flag
; *** PIE1 Bits
TMR1IE equ 0 ; Timer 1 Interrupt Enable
TMR2IE equ 1 ; Timer 2 Interrupt Enable
CCP1IE equ 2 ; CCP 1 Interrupt Enable
SSPIE equ 3 ; SSP Interrupt Enable
TXIE equ 4 ; ASP Transmit Interrupt Enable
RCIE equ 5 ; ASP Receive Interrupt Enable
ADIE equ 6 ; A/D Interrupt Enable
PSPIE equ 7 ; PSP Interrupt Enable
; *** PIE2 Bits
CCP2IE equ 0 ; CCP 2 Interrupt Enable
BCLIE equ 3 ; Bus Collision Interrupt Enable
EEIE equ 4 ; EEPROM Interrupt Enable
; *** PCON Bits
BOR equ 0 ; Brown-Out Reset Flag
POR equ 1 ; Power-On Reset Flag
; *** SSPCON2 Bits
SEN equ 0
RSEN equ 1
PEN equ 2
RCEN equ 3
ACKEN equ 4
ACKDT equ 5
ACKSTAT equ 6
GCEN equ 7
; *** SSPSTAT Bits
BF equ 0 ; SSP Buffer Full Flag
UA equ 1 ; SSP I2C Update Address Flag
R_W equ 2 ; SSP I2C Read/Write Status
S equ 3 ; SSP I2C Start Flag
P equ 4 ; SSP I2C Stop Flag
D_A equ 5 ; SSP I2C Data/Address Flag
CKE equ 6 ; SSP SPI Clock Edge Select
SMP equ 7 ; SSP SPI Data Input Sample Phase
; *** TXSTA Bits
TX9D equ 0 ; ASP Transmit 9th Bit
TRMT equ 1 ; ASP Transmit Shift Register Empty
BRGH equ 2 ; ASP High Baud Rate Select
SYNC equ 4 ; ASP Mode Select
TXEN equ 5 ; ASP Transmit Enable
TX9 equ 6 ; ASP Transmit Data Length Select
CSRC equ 7 ; ASP Clock Source Select
; *** ADCON1 Bits
PCFG0 equ 0 ; Port A Configuration (3 Bits)
PCFG1 equ 1
PCFG2 equ 2
PCFG3 equ 3
ADFM equ 7 ; A/D Result Format Select
; *** EECON1 Bits
RD equ 0 ; EEPROM Read Control
WR equ 1 ; EEPROM Write Control
WREN equ 2 ; EEPROM Write Enable
WRERR equ 3 ; EEPROM Write Error Flag
EEPGD equ 7 ; EEPROM Program / Data Select
LIST
