Saludos,
Pues le comento que estoy realizando una implementación de un sistema que ordene una serie de 16 numeros de 8 bits
cada uno, todo va bien, bueno la simulación la realizo en active-HDL y no hay problemas pero al intentar sintetizarlo en
el ISE de Xilinx me genera el siguiente error:
Analyzing Entity <ordenamiento> in library <work> (Architecture <burbble_sort>).
ERROR:Portability:3 - This Xilinx application has run out of memory or has encountered a memory conflict. Current memory usage is 2091532 kb. Memory
problems may require a simple increase in available system memory, or possibly a fix to the software or a special workaround. To troubleshoot or remedy
the problem, first: Try increasing your system's RAM. Alternatively, you may try increasing your system's virtual memory or swap space. If this does not fix
the problem, please try the following
: Search the Answers Database at support.xilinx.com to locate information on this error message. If neither of the above resources produces an available
solution, please use Web Support to open a case with Xilinx Technical Support off of support.xilinx.com. As it is likely that this may be an unforeseen problem,
please be prepared to submit relevant design files if necessary.
Process "Synthesize" failed
Según el mensaje de error el problema es de memoria pero no veo donde puede estar la falla, asi que si alguien me puede
dar una pista o mejor aún decirme donde puede estar el error se los agradecere mucho.
El código es el siguiente:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity ordenamiento is
port(
datain : in std_logic_vector(7 downto 0);
dataout : out std_logic_vector(7 downto 0);
latchin : in std_logic;
latchout : in std_logic;
choice, rst : in std_logic
);
end ordenamiento;
architecture burbble_sort of ordenamiento is
subtype numero00 is std_logic_vector(7 downto 0);
type struct00 is array (0 to 15) of numero00;
signal i : integer := 0;
begin
process(datain, latchin, latchout, rst, choice)
variable memoria00 : struct00;
variable temp : numero00 := "00000000";
begin
if(Rst = '1') then
i <= 0;
for j in 0 to 9 loop
memoria00(j) := (others => '0');
end loop;
elsif(latchin'event and latchin = '1' and i <= 9) then
memoria00(i) := datain;
dataout <= datain;
i <= i + 1;
elsif(choice'event and choice = '1') then
for j in 0 to 9 loop
for k in 0 to 8 loop
if(memoria00(k) > memoria00(k+1))then
temp := memoria00(k+1);
memoria00(k+1) := memoria00(k);
memoria00(k) := temp;
end if;
end loop;
end loop;
i <= 0;
elsif(latchout'event and latchout = '1') then
dataout <= memoria00(i);
if(i < 9) then
i <= i+1;
end if;
end if;
end process;
end burbble_sort;
Gracias
