/** ###################################################################
** THIS COMPONENT MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
** Filename : Cpu.C
** Project : delay_con_PE
** Processor : MC9S08SH8CPJ
** Component : MC9S08SH8_20
** Version : Component 01.007, Driver 01.35, CPU db: 3.00.062
** Datasheet : MC9S08SH8 Rev. 3 6/2008
** Compiler : CodeWarrior HCS08 C Compiler
** Date/Time : 26/05/2012, 12:43 p.m.
** Abstract :
** This bean "MC9S08SH8_20" contains initialization of the
** CPU and provides basic methods and events for CPU core
** settings.
** Settings :
**
** Contents :
** EnableInt - void Cpu_EnableInt(void);
** DisableInt - void Cpu_DisableInt(void);
** Delay100US - void Cpu_Delay100US(word us100);
**
** Copyright : 1997 - 2009 Freescale Semiconductor, Inc. All Rights Reserved.
**
** http : www.freescale.com
** mail : support@freescale.com
** ###################################################################*/
/* MODULE Cpu. */
#pragma MESSAGE DISABLE C4002 /* WARNING C4002: Result not used is ignored */
#include "PE_Types.h"
#include "PE_Error.h"
#include "PE_Const.h"
#include "IO_Map.h"
#include "Events.h"
#include "Cpu.h"
/* Global variables */
volatile byte CCR_reg; /* Current CCR register */
/*
** ===================================================================
** Method : Cpu_Interrupt (component MC9S08SH8_20)
**
** Description :
** The method services unhandled interrupt vectors.
** This method is internal. It is used by Processor Expert only.
** ===================================================================
*/
ISR(Cpu_Interrupt)
{
/* This code can be changed using the CPU bean property "Build Options / Unhandled int code" */
asm(BGND);
}
/*
** ===================================================================
** Method : Cpu_DisableInt (component MC9S08SH8_20)
**
** Description :
** Disables maskable interrupts
** Parameters : None
** Returns : Nothing
** ===================================================================
*/
/*
void Cpu_DisableInt(void)
** This method is implemented as macro in the header module. **
*/
/*
** ===================================================================
** Method : Cpu_EnableInt (component MC9S08SH8_20)
**
** Description :
** Enables maskable interrupts
** Parameters : None
** Returns : Nothing
** ===================================================================
*/
/*
void Cpu_EnableInt(void)
** This method is implemented as macro in the header module. **
*/
/*
** ===================================================================
** Method : Cpu_Delay100US (component MC9S08SH8_20)
**
** Description :
** This method realizes software delay. The length of delay
** is at least 100 microsecond multiply input parameter
** [us100]. As the delay implementation is not based on real
** clock, the delay time may be increased by interrupt
** service routines processed during the delay. The method
** is independent on selected speed mode.
** Parameters :
** NAME - DESCRIPTION
** us100 - Number of 100 us delay repetitions.
** Returns : Nothing
** ===================================================================
*/
#pragma NO_ENTRY
#pragma NO_EXIT
#pragma MESSAGE DISABLE C5703
void Cpu_Delay100US(word us100)
{
asm {
loop:
pshh
pshx /* (2 c: 250 ns) backup X */
ldhx #$0061 /* (3 c: 375 ns) number of iterations */
label0:
aix #-1 /* (2 c: 250 ns) decrement H:X */
cphx #0 /* (3 c: 375 ns) compare it to zero */
bne label0 /* (3 c: 375 ns) repeat 97x */
pulx /* (3 c: 375 ns) restore X */
pulh /* (3 c: 375 ns) restore H */
nop /* (1 c: 125 ns) wait for 1 c */
nop /* (1 c: 125 ns) wait for 1 c */
nop /* (1 c: 125 ns) wait for 1 c */
/* 100 us delay block end */
aix #-1 /* us100 parameter is passed via H:X registers */
cphx #0
bne loop /* next loop */
rts /* return from subroutine */
}
/* Restore MISRA rule 19 checking - Octal constant used */
/*lint +esym( 960, 19) */
/* Restore MISRA rule 55 checking - Non-case label used */
/*lint +esym( 961, 55) */
}
/*
** ===================================================================
** Method : _EntryPoint (component MC9S08SH8_20)
**
** Description :
** Initializes the whole system like timing and so on. At the end
** of this function, the C startup is invoked to initialize stack,
** memory areas and so on.
** This method is internal. It is used by Processor Expert only.
** ===================================================================
*/
extern void _Startup(void); /* Forward declaration of external startup function declared in file Start12.c */
#pragma NO_FRAME
#pragma NO_EXIT
void _EntryPoint(void)
{
/* ### MC9S08SH8_20 "Cpu" init code ... */
/* PE initialization code after reset */
/* Common initialization of the write once registers */
/* SOPT1: COPT=0,STOPE=0,??=0,??=0,IICPS=0,BKGDPE=1,RSTPE=0 */
setReg8(SOPT1, 0x02);
/* SPMSC1: LVWF=0,LVWACK=0,LVWIE=0,LVDRE=1,LVDSE=1,LVDE=1,??=0,BGBE=0 */
setReg8(SPMSC1, 0x1C);
/* SPMSC2: ??=0,??=0,LVDV=0,LVWV=0,PPDF=0,PPDACK=0,??=0,PPDC=0 */
setReg8(SPMSC2, 0x00);
/* System clock initialization */
if (*(unsigned char*)0xFFAF != 0xFF) { /* Test if the device trim value is stored on the specified address */
ICSTRM = *(unsigned char*)0xFFAF; /* Initialize ICSTRM register from a non volatile memory */
ICSSC = *(unsigned char*)0xFFAE; /* Initialize ICSSC register from a non volatile memory */
}
/* ICSC1: CLKS=0,RDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
setReg8(ICSC1, 0x06); /* Initialization of the ICS control register 1 */
/* ICSC2: BDIV=1,RANGE=0,HGO=0,LP=0,EREFS=0,ERCLKEN=0,EREFSTEN=0 */
setReg8(ICSC2, 0x40); /* Initialization of the ICS control register 2 */
while(!ICSSC_IREFST) { /* Wait until the source of reference clock is internal clock */
}
/* GNGC: GNGPS7=0,GNGPS6=0,GNGPS5=0,GNGPS4=0,GNGPS3=0,GNGPS2=0,GNGPS1=0,GNGEN=0 */
setReg8(GNGC, 0x00);
/*** End of PE initialization code after reset ***/
__asm jmp _Startup ; /* Jump to C startup code */
}
/*
** ===================================================================
** Method : PE_low_level_init (component MC9S08SH8_20)
**
** Description :
** Initializes beans and provides common register initialization.
** The method is called automatically as a part of the
** application initialization code.
** This method is internal. It is used by Processor Expert only.
** ===================================================================
*/
void PE_low_level_init(void)
{
/* Common initialization of the CPU registers */
/* PTASE: PTASE4=0,PTASE3=0,PTASE2=0,PTASE1=0,PTASE0=0 */
clrReg8Bits(PTASE, 0x1F);
/* PTBSE: PTBSE7=0,PTBSE6=0,PTBSE5=0,PTBSE4=0,PTBSE3=0,PTBSE2=0,PTBSE1=0,PTBSE0=0 */
setReg8(PTBSE, 0x00);
/* PTCSE: PTCSE3=0,PTCSE2=0,PTCSE1=0,PTCSE0=0 */
clrReg8Bits(PTCSE, 0x0F);
/* PTADS: ??=0,??=0,??=0,PTADS4=1,PTADS3=1,PTADS2=1,PTADS1=1,PTADS0=1 */
setReg8(PTADS, 0x1F);
/* PTBDS: PTBDS7=1,PTBDS6=1,PTBDS5=1,PTBDS4=1,PTBDS3=1,PTBDS2=1,PTBDS1=1,PTBDS0=1 */
setReg8(PTBDS, 0xFF);
/* PTCDS: ??=0,??=0,??=0,??=0,PTCDS3=1,PTCDS2=1,PTCDS1=1,PTCDS0=1 */
setReg8(PTCDS, 0x0F);
/* ### Shared modules init code ... */
__EI(); /* Enable interrupts */
}
/* Initialization of the CPU registers in FLASH */
/* NVPROT: FPS7=1,FPS6=1,FPS5=1,FPS4=1,FPS3=1,FPS2=1,FPS1=1,FPDIS=1 */
const unsigned char NVPROT_INIT @0x0000FFBD = 0xFF;
/* NVOPT: KEYEN=0,FNORED=1,??=1,??=1,??=1,??=1,SEC01=1,SEC00=0 */
const unsigned char NVOPT_INIT @0x0000FFBF = 0x7E;
/* END Cpu. */
/*
** ###################################################################
**
** This file was created by Processor Expert 3.07 [04.34]
** for the Freescale HCS08 series of microcontrollers.
**
** ###################################################################
*/
