Buen día séñores estoy tratando de manejar el DAC del dsPIC33FJ64GP802 pero lo trate se simular con el MPLAB SIM y no me funcionó, digo que no me funcionó pues no me entra a la interrupción del DAC , no se me activa la bandera de interrupción (DAC1RIF) cuando la FIFO no esta llena, quería saber si se puede simular?
Si la respuesta es SÍ, Les voy a mostrar el código... para que me regalen unos segundos y lo revisen...
#include "p33FJ64GP802.h"
//CONFIGURATION BITS
_FBS( BWRP_WRPROTECT_OFF & BSS_NO_FLASH & RBS_NO_RAM )
_FSS( RSS_NO_RAM & SSS_NO_FLASH & SWRP_WRPROTECT_OFF )
_FGS( GSS_OFF & GCP_OFF & GWRP_OFF )
_FOSCSEL(FNOSC_PRIPLL & IESO_ON); // Primary oscillator (XT, HS, EC) w/ PLL, Two-speed Oscillator Startup : Enabled
_FOSC(FCKSM_CSDCMD & IOL1WAY_OFF & OSCIOFNC_OFF & POSCMD_XT ); // Clock switching and clock monitor:Disabled & Single configuration for remappable I/O:Disabled & OSC2 is clock O/P & XT oscillator
_FWDT( FWDTEN_OFF & WINDIS_OFF )
_FPOR( ALTI2C_OFF & FPWRT_PWR128 )
_FICD( BKBUG_ON & COE_ON & JTAGEN_OFF & ICS_PGD1 )
unsigned int signal[5] = {32768, 63384, 54592, 17708, 209};
int i = 0;
int main (void)
{
// Oscillator Special Function Control Registers
// Configure Oscillator to operate the device at 40MIPS
// Fosc= Fin*M/(N1*N2), Fcy=Fosc/2 (XT=10MHz)
// CLOCK DIVISOR REGISTER
CLKDIVbits.PLLPRE= 0; //PLL Phase Detector Input Divider bits (also denoted as "N1", PLL prescaler) N2=2
CLKDIVbits.PLLPOST= 0; //PLL VCO Output Divider Select bits (also denoted as "N2", PLL postscaler) N1=2
//CLKDIVbits.FRCDIV= 0; //Internal Fast RC Oscillator Postscaler bits
CLKDIVbits.DOZEN= 0; //DOZE Mode Enable bit
CLKDIVbits.DOZE= 0; //Processor Clock Reduction Select bits =FCY/1
CLKDIVbits.ROI= 0; //Recover on Interrupt bit 0 = Interrupts have no effect on the DOZEN bit
//PLL FEEDBACK DIVISOR REGISTER
PLLFBD=30; //PLL Feedback Divisor bits (also denoted as "M", PLL multiplier) M=32
//FRC Oscillator Tuning Register
//OSCTUNbits.TUN=0b000000; //FRC Oscillator Tuning bits = Center frequency (7.37 MHz nominal)
//AUXILIARY CONTROL REGISTER
ACLKCONbits.SELACLK = 0; //Select Auxiliary Clock Source for Auxiliary Clock Divider 0 = PLLCLK
ACLKCONbits.AOSCMD = 0b00; //Auxiliary Oscillator Mode 00 = Auxiliary Oscillator Disabled
ACLKCONbits.APSTSCLR = 0b111; //Auxiliary Clock Output Divider 000 = /1
//ACLKCONbits.ASRCSEL = 1; //Select Reference Clock Source for Auxiliary Clock 1 = POSCCLK
//DAC STATUS REGISTER
DAC1STATbits.ROEN = 1; //Right Channel DAC output enable 1 = enabled
//DAC1STATBITS.LOEN=; //Left Channel DAC output enable
DAC1STATbits.RITYPE = 0; //Right Channel Type of Interrupt 0 = Interrupt if FIFO is NOT FULL.
//DAC1STATBITS.LITYPE=; //Left Channel Type of Interrupt
//DAC1STATBITS.REMPTY=; //Status, Right Channel Data input FIFO is EMPTY
//DAC1STATBITS.LEMPTY=; //Status, Left Channel Data input FIFO is EMPTY
//DAC1STATBITS.RFULL=; //Status, Right Channel Data input FIFO is FULL
//DAC1STATBITS.LFULL=; //Status, Left Channel Data input FIFO is FULL
DAC1STATbits.RMVOEN = 0; //Right Channel Midpoint DAC output voltage enable 0 = disabled
//DAC1STATBITS.LMVOEN=; //Left Channel Midpoint DAC output voltage enable
//DAC CONTROL REGISTER
DAC1CONbits.DACFDIV = 3; //DAC Clock Divider 3 = /4
DAC1CONbits.FORM = 0; //Data Format Select bit 0 = Unsigned integer
DAC1CONbits.AMPON = 1; //1 = Analog Output Amplifier is enabled during Sleep Mode/Stop-in Idle mode
DAC1CONbits.DACSIDL = 0; //Stop in Ideal Mode bit 0 = Continue module operation in Idle mode.
DAC1CONbits.DACEN = 1; //DAC1 Enable bit Enables module
DAC1DFLT = 0; //DAC DEFAULT DATA REGISTER
IFS4bits.DAC1RIF = 0; /* Clear Right Channel Interrupt Flag */
//IFS4bits.DAC1LIF = 0; /* Clear Left Channel Interrupt Flag */
IEC4bits.DAC1RIE = 1; /* Right Channel Interrupt Enabled */
//IEC4bits.DAC1LIE = 1; /* Left Channel Interrupt Enabled */
// PLLCLK/SELACLK/DACFDIV = DACCLK
// 80 MHz/1/4 = 20 MHz
// Fs = 78.125 KHz
while (1)
{
if (i == 5)
{
i = 0;
}
}
}
void __attribute__((interrupt, auto_psv))_DAC1RInterrupt(void)
{
DAC1RDAT = signal; /* User Code to Write to FIFO Goes Here */
i = i + 1;
IFS4bits.DAC1RIF = 0; /* Clear Right Channel Interrupt Flag */
}
