Algoritmo para haceer una division en vhdl

[androx]

Hola a todos!!!

Me gustaría saber cómo puedo hacer una división en VHDL.Espero me puedan ayudar

Muchas gracias

[androx]

He encontrado un algritmo para hacer una división,el problema es que no se muy bien como hacer el test bench.El código es este:


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity divisor is
 port (
        GO: in STD_LOGIC;
        IN_N: in STD_LOGIC_VECTOR (7 downto 0);
        IN_D: in STD_LOGIC_VECTOR (7 downto 0);
        EXT_CLK: in STD_LOGIC;
        OUT_Q: out STD_LOGIC_VECTOR (7 downto 0);
        OUT_R: out STD_LOGIC_VECTOR (7 downto 0));

end divisor;

architecture Behavioral of divisor is

   signal X: STD_LOGIC_VECTOR(16 downto 0);
   signal D: STD_LOGIC_VECTOR(8 downto 0);
   signal ND: STD_LOGIC_VECTOR(8 downto 0);
   signal cycle: INTEGER RANGE 0 to 18;

begin
   D <= '0' & IN_D;
  ND <= '0' & (-IN_D);
  OUT_R <= X(15 downto ;
  OUT_Q <= X(7 downto 0);
 
  process is
    variable sum: STD_LOGIC_VECTOR(8 downto 0);
  begin
    wait on EXT_CLK until EXT_CLK = '1';
    if (GO = '1') then
      cycle <= 1;
      X <= "000000000" & IN_N;
    elsif (cycle = 0) then
    elsif (cycle = 17) then
      if (X(0) = '0') then
        X(15 downto <= X(15 downto + D(7 downto 0);
      end if;
      cycle <= 0;
    elsif (cycle mod 2 = 1) then
      X <= '0' & X(14 downto 0) & '0';
      cycle <= cycle + 1;
    else
      if ((X(1) = '1') or (cycle = 2)) then
        sum := X(16 downto + ND;
      else
        sum := X(16 downto + D;
      end if;
      X(15 downto <= sum(7 downto 0);
      X(0) <= sum(;
      cycle <= cycle + 1;
    end if ;
  end process;


end Behavioral;



Y el código del test bench que he hecho yo es el siguiente:


LIBRARY ieee;
  USE ieee.std_logic_1164.ALL;
  USE ieee.numeric_std.ALL;

  ENTITY testbench IS
  END testbench;

  ARCHITECTURE behavior OF testbench IS

  -- Component Declaration
          COMPONENT divisor
          PORT(
                  GO : IN std_logic;
                  IN_N : IN std_logic_vector(7 downto 0);       
                  IN_D : IN std_logic_vector(7 downto 0);
                  EXT_CLK: IN std_logic;
                  OUT_Q: out STD_LOGIC_VECTOR (7 downto 0);
                    OUT_R: out STD_LOGIC_VECTOR (7 downto 0));
          END COMPONENT;

         --Entradas
          SIGNAL EXT_CLK :  std_logic:='0';
          SIGNAL GO :  std_logic :='1';
          SIGNAL IN_N :  std_logic_vector(7 downto 0) := "00001110";
          SIGNAL IN_D:  std_logic_vector(7 downto 0) := "00000010";

         --Outputs

          SIGNAL OUT_Q: std_logic_vector(7 downto 0);
          SIGNAL OUT_R: std_logic_vector(7 downto 0);

         

  BEGIN

  -- Component Instantiation
          uut: divisor PORT MAP(
                  EXT_CLK => EXT_CLK,
                  GO => GO,
                  IN_N => IN_N,
                  IN_D => IN_D,
                  OUT_Q => OUT_Q,
                  OUT_R => OUT_R);


  --  Test Bench Statements
     tb : PROCESS
     BEGIN

        wait for 100 ns; -- wait until global set/reset completes

        -- Add user defined stimulus here

        wait; -- will wait forever
     END PROCESS tb;
  --  End Test Bench

  END;



Pero al probarlo las salidas OUT_Q y OUT_R toman los valores UUUUUUUU y no se por qué es

Gracias

[antoniof]

  --  Test Bench Statements
     tb : PROCESS
     BEGIN

        wait for 100 ns; -- wait until global set/reset completes

        -- Add user defined stimulus here

        ******************************
        Aqui debes ir modificando las señales de entrada al módulo divisor.
        ******************************


        wait; -- will wait forever
     END PROCESS tb;
  --  End Test Bench

  END;

El test bench lo que hace es mover las señales de entrada al módulo divisor. Pero tu aqui no tienes señales moviendose por lo que las salidas están indeterminadas 'UUUUU'