Hola a tod@s, tengo un pequeño problema y quisiera saber si alguien me puede ayudar, estoy programando en VHDL y al compilar me da un error, alguien sabria decirme como puedo solucionarlo.
HDLParsers:164 - "D:/ProZeus/Codi VHDL/Generador PWM/Divisor_Rellotge.vhd" Line 32. parse error, unexpected INTEGER_LITERAL, expecting IDENTIFIER
HDLParsers:3481 - Library work has no units. Did not save reference file "xst/work/hdllib.ref" for it.
El error proviene del siguiente codigo
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Divisor_Rellotge is
Port ( Rellotge_in : in std_logic;
2_5us : out std_logic;
20ms : out std_logic;
variable c_2_5us : std_logic_vector ( 7 downto 0);
variable c_20ms : std_logic_vector ( 10 downto 0));
end Divisor_Rellotge;
architecture Behavioral of Divisor_Rellotge is
begin
process (Rellotge_in)
begin
2_5us <= '0';
20ms <= '0';
if (Rellotge_in'event and Rellotge_in = '1')
c_2_5us <= c_2_5us + 1;
c_20ms <= c_20ms + 1;
end if
if (c_2_5us = '125')
c_2.5us <= '0';
2_5us = '1';
c_20ms <= c_20ms + '1';
end if
if (c_20ms = '1000')
c_20ms <= '0';
20ms <= '1';
end if
end process
end Behavioral;
