Hola, tengo que hacer el diseño de una máquina de estados finitos capaz de detectar la secuencia '0110' de bits en su única entrada de datos. En cuanto la secuencia sea detectada se activará una salida indicando que se ha reconocido la secuencia buscada.
El código que he hecho compila perfectamente, pero a la hora de simular pone:
error: failed to initialize the simulator
Error: <300c8> During elaboration.
Failed to open the design data for the default bound architecture of root ENTITY SEQDEC_TB.
Error: <30000> During elaboration.
Elaborator Error
No se muy bien que hacer, os pongo el codigo por si acaso.
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la entidad:
library ieee;
use ieee.std_logic_1164.all;
entity seqdec_en is
port (clock, reset, i: in std_logic;
o: out std_logic);
end seqdec_en;
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la arquitectura funcional:
architecture functional of seqdec_en is
type estados is (s0, s1, s2, s3, s4);
signal ns, ps: estados;
begin
PROCESS (i, ps)
begin
case ps is
when s0=> IF i= '0' THEN ns<= s1; o<= '0';
ELSE ns<= s0; o<= '0';
end IF;
when s1=> IF i= '0' THEN ns<= s1; o<= '0';
ELSE ns<= s0; o<= '0';
end IF;
when s2=> IF i= '0' THEN ns<= s1; o<= '0';
ELSE ns<= s0; o<= '0';
end IF;
when s3=> IF i= '0' THEN ns<= s4; o<= '0';
ELSE ns<= s0; o<= '0';
end IF;
when s4=> IF i= '0' THEN ns<= s1; o<= '1';
ELSE ns<= s0; o<= '1';
end IF;
end case;
end PROCESS;
PROCESS (clock, reset)
begin
IF reset= '1' THEN
ps<= s0;
ELSIF rising_edge(clock) THEN
ps<= ns;
end IF;
end PROCESS;
end functional;
-------------------------------------------------------------------------
la arquitectura estructural ( con su flip flop correspondiente );
library ieee;
use ieee.std_logic_1164.all;
entity flipflop_d is
port (
clock, reset : in std_logic;
d : in std_logic;
q, notq : out std_logic);
end flipflop_d;
architecture functional of flipflop_d is
begin
process (clock, reset)
variable aux : std_logic;
begin
if reset = '1' then
aux := '0';
elsif clock'event and clock = '1' then
aux := d;
end if;
q <= aux;
notq <= not aux;
end process;
end functional;
----------------------------------------------
architecture structural of seqdec_en is
signal d0, d1, d2, q0, ntq0, q1, ntq1, q2, ntq2: std_logic;
begin
d0<= (q1 AND ntq0) OR (ntq1 AND NOT i);
d1<= (q1 AND ntq0 AND i) OR (ntq1 AND q0 AND i);
d2<= (q1 AND q0 AND NOT i);
flipflop0: entity work.flipflop_d port map (clock, reset, d0, q0, ntq0);
flipflop1: entity work.flipflop_d port map (clock, reset, d1, q1, ntq1);
flipflop2: entity work.flipflop_d port map (clock, reset, d2, q2, ntq2);
o<= q2;
end structural;
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y por ultimo el testbench:
library ieee;
use ieee.std_logic_1164.all;
entity seqdec_tb is
end seqdec_tb;
architecture testbench of seqdec_en is
signal p: std_logic:= '0';
signal clk: std_logic:= '0';
signal rst: std_logic:= '0';
signal ok: std_logic:= '0';
signal o1,o2 : std_logic;
begin
clk<= NOT clock after 5ns;
rst<= '1' after 1ns;
p<= '1' after 10ns, '0' after 20ns, '0' after 30ns, '1' after 40ns, '1' after 50ns, '0' after 60ns, '0' after 70ns, '1' after 80ns, '0' after 90ns, '0' after 100ns, '1' after 110ns, '0' after 120ns, '0' after 130ns, '1' after 140ns, '1' after 50ns, '0' after 160ns;
fu: entity work.seqdec_en (functional) port map (clk, rst, p, o1);
st: entity work.seqdec_en (structural) port map (clk, rst, p, o2);
ok<= o1 XNOR o2;
end testbench;
[code]
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por favor, os agradeceria mucho vuestra ayuda porque realmente necesito qu efuncione, y no entiendo que pasa
muachas graciias!
