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;********************************************************************************************; FUSE OPTIONS (SOURCE: P18F2550.INC);; PLL Prescaler Selection bits:; CONFIG PLLDIV = 1 ;No prescale (4 MHz oscillator input drives PLL directly); CONFIG PLLDIV = 2 ;Divide by 2 (8 MHz oscillator input); CONFIG PLLDIV = 3 ;Divide by 3 (12 MHz oscillator input); CONFIG PLLDIV = 4 ;Divide by 4 (16 MHz oscillator input) CONFIG PLLDIV = 5 ;Divide by 5 (20 MHz oscillator input); CONFIG PLLDIV = 6 ;Divide by 6 (24 MHz oscillator input); CONFIG PLLDIV = 10 ;Divide by 10 (40 MHz oscillator input); CONFIG PLLDIV = 12 ;Divide by 12 (48 MHz oscillator input);; CPU System Clock Postscaler: CONFIG CPUDIV = OSC1_PLL2 ;[OSC1/OSC2 Src: /1][96 MHz PLL Src: /2]; CONFIG CPUDIV = OSC2_PLL3 ;[OSC1/OSC2 Src: /2][96 MHz PLL Src: /3]; CONFIG CPUDIV = OSC3_PLL4 ;[OSC1/OSC2 Src: /3][96 MHz PLL Src: /4]; CONFIG CPUDIV = OSC4_PLL6 ;[OSC1/OSC2 Src: /4][96 MHz PLL Src: /6];; USB Clock Selection bit (used in Full Speed USB mode only; UCFG:FSEN = 1):; CONFIG USBDIV = 1 ;USB clock source comes directly from the primary oscillator block with no postscale CONFIG USBDIV = 2 ;USB clock source comes from the 96 MHz PLL divided by 2;; Oscillator Selection bits:; CONFIG FOSC = XT_XT ;XT oscillator, XT used by USB; CONFIG FOSC = XTPLL_XT ;XT oscillator, PLL enabled, XT used by USB; CONFIG FOSC = ECIO_EC ;External clock, port function on RA6, EC used by USB; CONFIG FOSC = EC_EC ;External clock, CLKOUT on RA6, EC used by USB; CONFIG FOSC = ECPLLIO_EC ;External clock, PLL enabled, port function on RA6, EC used by USB; CONFIG FOSC = ECPLL_EC ;External clock, PLL enabled, CLKOUT on RA6, EC used by USB CONFIG FOSC = INTOSCIO_EC ;Internal oscillator, port function on RA6, EC used by USB; CONFIG FOSC = INTOSC_EC ;Internal oscillator, CLKOUT on RA6, EC used by USB; CONFIG FOSC = INTOSC_XT ;Internal oscillator, XT used by USB; CONFIG FOSC = INTOSC_HS ;Internal oscillator, HS used by USB; CONFIG FOSC = HS ;HS oscillator, HS used by USB; CONFIG FOSC = HSPLL_HS ;HS oscillator, PLL enabled, HS used by USB;; Fail-Safe Clock Monitor Enable bit: CONFIG FCMEN = OFF ;Fail-Safe Clock Monitor disabled; CONFIG FCMEN = ON ;Fail-Safe Clock Monitor enabled;; Internal/External Oscillator Switchover bit: CONFIG IESO = OFF ;Oscillator Switchover mode disabled; CONFIG IESO = ON ;Oscillator Switchover mode enabled;; Power-up Timer Enable bit: CONFIG PWRT = ON ;PWRT enabled; CONFIG PWRT = OFF ;PWRT disabled;; Brown-out Reset Enable bits: CONFIG BOR = OFF ;Brown-out Reset disabled in hardware and software; CONFIG BOR = SOFT ;Brown-out Reset enabled and controlled by software (SBOREN is enabled); CONFIG BOR = ON_ACTIVE ;Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled); CONFIG BOR = ON ;Brown-out Reset enabled in hardware only (SBOREN is disabled);; Brown-Out Voltage bits:; CONFIG BORV = 0 ; 4.59 v; CONFIG BORV = 1 ; 4.33 v CONFIG BORV = 2 ; 2.79 v; CONFIG BORV = 3 ; 2.05 v;; USB Voltage Regulator Enable bit:; CONFIG VREGEN = OFF ;USB voltage regulator disabled CONFIG VREGEN = ON ;USB voltage regulator enabled;; Watchdog Timer Enable bit: CONFIG WDT = OFF ;HW Disabled - SW Controlled; CONFIG WDT = ON ;HW Enabled - SW Disabled;; Watchdog Timer Postscale Select bits:; CONFIG WDTPS = 1 ;1:1; CONFIG WDTPS = 2 ;1:2; CONFIG WDTPS = 4 ;1:4; CONFIG WDTPS = 8 ;1:8; CONFIG WDTPS = 16 ;1:16; CONFIG WDTPS = 32 ;1:32; CONFIG WDTPS = 64 ;1:64; CONFIG WDTPS = 128 ;1:128; CONFIG WDTPS = 256 ;1:256; CONFIG WDTPS = 512 ;1:512; CONFIG WDTPS = 1024 ;1:1024; CONFIG WDTPS = 2048 ;1:2048; CONFIG WDTPS = 4096 ;1:4096; CONFIG WDTPS = 8192 ;1:8192; CONFIG WDTPS = 16384 ;1:16384 CONFIG WDTPS = 32768 ;1:32768;; MCLR Pin Enable bit:; CONFIG MCLRE = OFF ;RE3 input pin enabled; MCLR disabled CONFIG MCLRE = ON ;MCLR pin enabled; RE3 input pin disabled;; Low-Power Timer 1 Oscillator Enable bit:; CONFIG LPT1OSC = OFF ;Timer1 configured for higher power operation CONFIG LPT1OSC = ON ;Timer1 configured for low-power operation;; PORTB A/D Enable bit: CONFIG PBADEN = OFF ;PORTB<4:0> pins are configured as digital I/O on Reset; CONFIG PBADEN = ON ;PORTB<4:0> pins are configured as analog input channels on Reset;; CCP2 MUX bit:; CONFIG CCP2MX = OFF ;CCP2 input/output is multiplexed with RB3 CONFIG CCP2MX = ON ;CCP2 input/output is multiplexed with RC1;; Stack Full/Underflow Reset Enable bit: CONFIG STVREN = OFF ;Stack full/underflow will not cause Reset; CONFIG STVREN = ON ;Stack full/underflow will cause Reset;; Single-Supply ICSP Enable bit: CONFIG LVP = OFF ;Single-Supply ICSP disabled; CONFIG LVP = ON ;Single-Supply ICSP enabled;; Extended Instruction Set Enable bit: CONFIG XINST = OFF ;Instruction set extension and Indexed Addressing mode disabled (Legacy mode); CONFIG XINST = ON ;Instruction set extension and Indexed Addressing mode enabled;; Background Debugger Enable bit:; CONFIG DEBUG = ON ;Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug CONFIG DEBUG = OFF ;Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins;; Code Protection bit Block 0:; CONFIG CP0 = ON ;Block 0 (000800-001FFFh) code-protected CONFIG CP0 = OFF ;Block 0 (000800-001FFFh) not code-protected;; Code Protection bit Block 1:; CONFIG CP1 = ON ;Block 1 (002000-003FFFh) code-protected CONFIG CP1 = OFF ;Block 1 (002000-003FFFh) not code-protected;; Code Protection bit Block 2:; CONFIG CP2 = ON ;Block 2 (004000-005FFFh) code-protected CONFIG CP2 = OFF ;Block 2 (004000-005FFFh) not code-protected;; Code Protection bit Block 3:; CONFIG CP3 = ON ;Block 3 (006000-007FFFh) code-protected CONFIG CP3 = OFF ;Block 3 (006000-007FFFh) not code-protected;; Boot Block Code Protection bit:; CONFIG CPB = ON ;Boot block (000000-0007FFh) code-protected CONFIG CPB = OFF ;Boot block (000000-0007FFh) not code-protected;; Data EEPROM Code Protection bit:; CONFIG CPD = ON ;Data EEPROM code-protected CONFIG CPD = OFF ;Data EEPROM not code-protected;; Write Protection bit Block 0:; CONFIG WRT0 = ON ;Block 0 (000800-001FFFh) write-protected CONFIG WRT0 = OFF ;Block 0 (000800-001FFFh) not write-protected;; Write Protection bit Block 1:; CONFIG WRT1 = ON ;Block 1 (002000-003FFFh) write-protected; CONFIG WRT1 = OFF ;Block 1 (002000-003FFFh) not write-protected;; Write Protection bit Block 2:; CONFIG WRT2 = ON ;Block 2 (004000-005FFFh) write-protected CONFIG WRT2 = OFF ;Block 2 (004000-005FFFh) not write-protected;; Write Protection bit Block 3:; CONFIG WRT3 = ON ;Block 3 (006000-007FFFh) write-protected CONFIG WRT3 = OFF ;Block 3 (006000-007FFFh) not write-protected;; Boot Block Write Protection bit:; CONFIG WRTB = ON ;Boot block (000000-0007FFh) write-protected CONFIG WRTB = OFF ;Boot block (000000-0007FFh) not write-protected;; Configuration Register;Write Protection bit:; CONFIG WRTC = ON ;Configuration registers (300000-3000FFh) write-protected CONFIG WRTC = OFF ;Configuration registers (300000-3000FFh) not write-protected;; Data EEPROM Write Protection bit:; CONFIG WRTD = ON ;Data EEPROM write-protected CONFIG WRTD = OFF ;Data EEPROM not write-protected;; Table Read Protection bit Block 0:; CONFIG EBTR0 = ON ;Block 0 (000800-001FFFh) protected from table reads executed in other blocks CONFIG EBTR0 = OFF ;Block 0 (000800-001FFFh) not protected from table reads executed in other blocks;; Table Read Protection bit Block 1:; CONFIG EBTR1 = ON ;Block 1 (002000-003FFFh) protected from table reads executed in other blocks CONFIG EBTR1 = OFF ;Block 1 (002000-003FFFh) not protected from table reads executed in other blocks;; Table Read Protection bit Block 2:; CONFIG EBTR2 = ON ;Block 2 (004000-005FFFh) protected from table reads executed in other blocks CONFIG EBTR2 = OFF ;Block 2 (004000-005FFFh) not protected from table reads executed in other blocks;; Table Read Protection bit Block 3:; CONFIG EBTR3 = ON ;Block 3 (006000-007FFFh) protected from table reads executed in other blocks CONFIG EBTR3 = OFF ;Block 3 (006000-007FFFh) not protected from table reads executed in other blocks;; Boot Block Table Read Protection:; CONFIG EBTRB = ON ;Boot block (000000-0007FFh) protected from table reads executed in other blocks CONFIG EBTRB = OFF ;Boot block (000000-0007FFh) not protected from table reads executed in other blocks;;********************************************************************************************
#define PORT_RX PORTCbits.RC7 #define PORT_TX PORTCbits.RC6 TRISCbits.TRISC7 = 1; TRISCbits.TRISC6 = 0; while(1) PORT_TX = PORT_RX;
Protoboard armado.*Le puse un regulador de 5V, ya que la batería me daba 6V y prefiero irme a lo seguro.*En la imagen, se observa el Tx del BT y el Tx del micro. El Tx del BT va al Rx del micro, y el Tx del micro, va al Rx del BT.