Hola otra vez.... he generado un multiplicador, con el core generator.... de una entrada de 8 bits y multiplicado por una constante (diez) y me genera este código que me resulta un poco raro......
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
Library XilinxCoreLib;
ENTITY multiplier IS
port (
clk: IN std_logic;
a: IN std_logic_VECTOR(7 downto 0);
q: OUT std_logic_VECTOR(11 downto 0));
END multiplier;
ARCHITECTURE multiplier_a OF multiplier IS
component wrapped_multiplier
port (
clk: IN std_logic;
a: IN std_logic_VECTOR(7 downto 0);
q: OUT std_logic_VECTOR(11 downto 0));
end component;
-- Configuration specification
for all : wrapped_multiplier use entity XilinxCoreLib.mult_gen_v7_0(behavioral)
generic map(
c_a_type => 1,
c_mem_type => 2,
c_has_sclr => 0,
c_reg_a_b_inputs => 1,
c_has_q => 1,
c_has_o => 0,
bram_addr_width => 9,
c_v2_speed => 0,
c_baat => 1,
c_output_hold => 0,
c_b_constant => 1,
c_has_loadb => 0,
c_has_b => 0,
c_use_luts => 1,
c_has_rdy => 0,
c_has_nd => 0,
c_pipeline => 0,
c_has_a_signed => 0,
c_b_type => 1,
c_sqm_type => 0,
c_standalone => 1,
c_enable_rlocs => 0,
c_b_value => "1010",
c_mult_type => 2,
c_has_aclr => 0,
c_has_swapb => 0,
c_has_load_done => 0,
c_out_width => 12,
c_mem_init_prefix => "mem",
c_b_width => 4,
c_a_width => 8,
c_has_rfd => 0,
c_sync_enable => 1,
c_has_ce => 0,
c_stack_adders => 1);
BEGIN
U0 : wrapped_multiplier
port map (
clk => clk,
a => a,
q => q);
END multiplier_a;
-- synopsys translate_on
Y cuando lo sintetizo me da error, así que estoy un poco perdido !! Podeis ayudarme por favor ????
