Os explico, lo he hecho por separado.......
EL primer fuente con todos los comportamientos de las entidades están aquí....
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity div25Mhz is --divisor de 25Mhz !!
Port ( CLK : in std_logic;
CLK1 : out std_logic);
end div25Mhz;
architecture Behavioral of div25Mhz is
begin
process (CLK)
variable CUENTA:std_logic_vector(1 downto 0):="00";--
begin
if clk"event and clk="1"then
--if CUENTA=2 then --CUANDO LLEGA UNA SEÑAL DE RELOJ
if CUENTA=2 then --VALE CUENTA 2?
CLK1<="1"; --SÍ , DAMOS UN PULSO
CUENTA:=(OTHERS=>"0"); --EMPEZAMOS OTRA VEZ
else --NO, SIGUE EN CERO E INCREMENTAMOS 1
CLK1<="0" ;
CUENTA:=CUENTA+ 1;
end if;
end if;
end process;
end Behavioral;
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity divkhz is --Divisor de 250Khz
Port ( clk : in std_logic;
salida : out std_logic);
end divkhz;
architecture Behavioral of divkhz is
begin
PROCESS(clk)
variable tmp :std_logic_vector(7 downto 0 ):="00000000";
BEGIN
IF(clk"EVENT AND clk="1") THEN
if tmp = 80 then
tmp := (others =>"0");
salida <= "1";
else
tmp := tmp+1;
salida <= "0";
end if;
END IF;
END PROCESS;
end Behavioral;
-------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- ------------------------------
Entity LCD_DRV is
-- ------------------------------
port( Clk : in std_logic; -- System Clock
Rst : in std_logic; -- asynchronous Reset, active high
Tick : in std_logic; -- Tick at 250 kHz (one clock cycle long)
Din : in std_logic_vector (7 downto 0); -- Input data
Dav : in std_logic; -- Write Data command (1 clock cycle)
Busy : out std_logic; -- "1" if device busy
-- LCD signals
Dout : inout std_logic_vector(7 downto 0); -- LCD data is a bidirectional bus...
Lcd_Sel : out std_logic; -- LCD register select
Lcd_Rw : out std_logic; -- LCD Read / nWrite
Lcd_En : out std_logic -- LCD Enable
);
end LCD_DRV;
-- ------------------------------
Architecture RTL of LCD_DRV is
-- ------------------------------
type State_type is (Boot, Initial, Display, Entrymode, Clear,
Address_set, Waiting, Verify, Putchar, Homecursor);
signal State : State_type;
-- Function set for 8-bit data transfer and 2-line display
constant SET : std_logic_vector(7 downto 0) := "00111100"; -- 0011 N F xx
-- Display ON, with cursor.**I set the last digit to one so the cursor does blink**
constant DON : std_logic_vector(7 downto 0) := "00001111";
-- Set Entry Mode to increment cursor automatically after each character displayed.
--**If the last digit is set to 1, then the whole display is shifted to the left.**
constant SEM : std_logic_vector(7 downto 0) := "00000110";
-- Clear screen command.
constant CLR : std_logic_vector(7 downto 0) := "00000001";
-- DD RAM address set
constant DDRAS : std_logic_vector(7 downto 0) := "10000000";
-- Home cursor
constant HOME1 : std_logic_vector(7 downto 0) := "00000010"; -- set addr to Beg of line 1
constant HOME2 : std_logic_vector(7 downto 0) := "11000000"; -- set addr to Beg of line 2
-- Timing Constants :
constant Big_delay : integer := 7500; -- 30 ms
constant Clr_delay : integer := 500; -- 2 ms
constant Small_delay : integer := 12; -- > 39 us after E down
constant En_delay : integer := 2;
constant LastPosition : integer := 16;
signal DavM : std_logic;
SIGNAL Dav : std_logic;
signal DataM : std_logic_vector (7 downto 0);
signal Position : integer range 0 to 32;
signal Count : integer range 0 to Big_delay;
begin
Lcd_Rw <= "0"; -- always in Write mode...
process (Clk, Rst)
begin
if Rst = "1" then
State <= Boot;
Position <= 0;
Count <= 0;
DavM <= "0";
Lcd_En <= "0";
Lcd_Sel <= "1";
Busy <= "1";
Dout <= (others=>"0");
elsif rising_edge(Clk) then
if Dav = "1" then
DavM <= "1";
DataM <= Din;
Busy <= "1";
end if;
if Tick = "1" then
case State is
when Boot => -- Power up wait 30 ms
Lcd_Sel <= "1";
Lcd_En <= "0";
Busy <= "1";
if Count = Big_delay then
Lcd_Sel <= "0";
Count <= 0;
State <= Initial;
else
Count <= Count + 1;
end if;
when Initial => -- Set Function & Mode
Dout <= SET;
Lcd_Sel <= "0";
if Count = 1 then
Lcd_En <= "1";
elsif Count = En_delay then
Lcd_En <= "0";
end if;
if Count = Small_delay then
State <= EntryMode;
Count <= 0;
else
Count <= Count+1;
end if;
when EntryMode => -- set Entry Mode,
Dout <= SEM;
Lcd_Sel <= "0";
if Count = 1 then
Lcd_En <= "1";
elsif Count = En_delay then
Lcd_En <= "0";
end if;
if Count = Small_delay then
State <= Display;
Count <= 0;
else
Count <= Count+1;
end if;
when Display => -- set Display ON
Dout <= DON;
Lcd_Sel <= "0";
if Count = 1 then
Lcd_En <= "1";
elsif Count = En_delay then
Lcd_En <= "0";
end if;
if Count = Small_delay then
State <= Clear;
Count <= 0;
else
Count <= Count+1;
end if;
when Clear => -- Clear the screen
Dout <= CLR;
Position <= 0;
Lcd_Sel <= "0";
if Count = 1 then
Lcd_En <= "1";
elsif Count = En_delay then
Lcd_En <= "0";
end if;
if Count = Clr_delay then
Count <= 0;
State <= Address_set;
else
Count <= Count+1;
end if;
when Address_set => -- DD RAM address set
Dout <= DDRAS;
Lcd_Sel <= "0";
if Count = 1 then
Lcd_En <= "1";
elsif Count = En_delay then
Lcd_En <= "0";
end if;
if Count = Small_delay then
State <= Waiting;
Count <= 0;
else
Count <= Count+1;
end if;
when Waiting => -- Waits for input
if DavM = "1" then
DavM <= "0";
State <= Verify;
Lcd_Sel <= "1";
else
Busy <= "0";
end if;
when Verify =>
if DataM = x"0C" then -- FormFeed => Clear Screen
State <= Clear;
elsif Position = 16 then
Dout <= HOME2;
State <= HomeCursor;
elsif Position = 32 then
Position <= 0;
Dout <= HOME1;
State <= HomeCursor;
else
Dout <= DataM;
State <= Putchar;
end if;
when Putchar => -- Display the character on the LCD
Lcd_Sel <= "1";
if Count = 1 then
Lcd_En <= "1";
elsif Count = En_delay then
Lcd_En <= "0";
end if;
if Count = Small_delay then
Position <= Position + 1;
Count <= 0;
State <= Waiting;
else
Count <= Count + 1;
end if;
when HomeCursor =>
Lcd_Sel <= "0";
if Count = 1 then
Lcd_En <= "1";
elsif Count = En_delay then
Lcd_En <= "0";
end if;
if Count = Clr_delay then
Dout <= DataM;
State <= Putchar;
Count <= 0;
else
Count <= Count+1;
end if;
end case;
end if;
end if;
end process;
end RTL;
----------------------------
--------------------------
---------------------------
-----------------------------
Aquí estaría el bloque con el que introduzco los datos.......
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity holamundo is
Port ( busy : in std_logic;
clk :in std_logic;
reset : in std_logic;
Salida : out std_logic_vector(7 downto 0));
end holamundo;
architecture Behavioral of holamundo is
signal clk1: std_logic ;
signal letra: std_logic_vector(3 downto 0);
begin
process (CLK)
variable CUENTA:std_logic_vector(24 downto 0):="0000000000000000000000000";--VARIABLE PARA CONTAR HASTA 50 MILL
begin
if clk"event and clk="1"then
--if CUENTA=250 then --CUANDO LLEGA UNA SEÑAL DE RELOJ
if CUENTA=250 then --VALE CUENTA 250?
CLK1<="1"; --SÍ , DAMOS UN PULSO
CUENTA:=(OTHERS=>"0"); --EMPEZAMOS OTRA VEZ
else --NO, SIGUE EN CERO E INCREMENTAMOS 1
CLK1<="0" ;
CUENTA:=CUENTA+ 1;
end if;
end if;
end process;
process (clk1)
begin
if clk1"event and clk1="1" then
if reset ="1" then
letra <= (others=>"0");
elsif letra =15 then
letra <= (others=>"0");
else
letra <= letra + 1;
end if;
end if;
end process;
process (letra)
begin
case letra is
when "0000" => salida<= "00100000";--espacio
when "0001" => salida<= "00100000";--espacio
when "0010" => salida<= "01001000"; -- H
when "0011" => salida<= "01001111"; -- O
when "0100" => salida<= "01001100"; -- L
when "0101" => salida<= "01000001"; -- A
when "0110" => salida<= "00100000";--espacio
when "0111" => salida<= "01001101"; -- M
when "1000" => salida<= "01010101"; -- U
when "1001" => salida<= "01001110"; -- N
when "1010" => salida<= "01000100"; -- D
when "1011" => salida<= "01001111"; -- O
when "1100" => salida<= "00100000";--espacio
when "1101" => salida<= "00100000";--espacio
when "1110" => salida<= "00100000";--espacio
when "1111" => salida<= "00100000";--espacio
when others => salida <=(others=>"0");
end case;
Dav <= "1";
end process;
end Behavioral;
--------------------------------------------------------------------------------
----------------------------------------------------------------------------------
--------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Y finalmente la conexión entre los dos bloques.......
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use work.componentes.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mapeado is
port( Clk : in std_logic; -- System Clock
Rst : in std_logic; -- asynchronous Reset, active high
--Tick : in std_logic; -- Tick at 250 kHz (one clock cycle long)
-- Din : in std_logic_vector (7 downto 0); -- Input data
--Dav : in std_logic; -- Write Data command (1 clock cycle)
Busy : out std_logic; -- "1" if device busy
-- LCD signals
Dout : inout std_logic_vector(7 downto 0); -- LCD data is a bidirectional bus...
Lcd_Sel : out std_logic; -- LCD register select
Lcd_Rw : out std_logic; -- LCD Read / nWrite
Lcd_En : out std_logic -- LCD Enable
);
end mapeado;
architecture Behavioral of mapeado is
SIGNAL CABLE1,CABLE2,CABLE4,CABLE5: std_logic ;
signal DAV: std_logic;
SIGNAL CABLE3: STD_LOGIC_VECTOR(7 DOWNTO 0);
COMPONENT div25Mhz
Port ( CLK : in std_logic;
CLK1 : out std_logic);
end COMPONENT;
----------------------------------
COMPONENT divkhz
Port ( clk : in std_logic;
salida : out std_logic);
end COMPONENT;
----------------------------------
COMPONENT LCD_DRV
port( Clk : in std_logic; -- System Clock
Rst : in std_logic; -- asynchronous Reset, active high
Tick : in std_logic; -- Tick at 250 kHz (one clock cycle long)
Din : in std_logic_vector (7 downto 0); -- Input data
Dav : in std_logic; -- Write Data command (1 clock cycle)
Busy : out std_logic; -- "1" if device busy
-- LCD signals
Dout : inout std_logic_vector(7 downto 0); -- LCD data is a bidirectional bus...
Lcd_Sel : out std_logic; -- LCD register select
Lcd_Rw : out std_logic; -- LCD Read / nWrite
Lcd_En : out std_logic -- LCD Enable
);
end COMPONENT;
-------------------------------------
COMPONENT holamundo
Port ( busy : in std_logic;
clk :in std_logic;
reset : in std_logic;
Salida : out std_logic_vector(7 downto 0));
END COMPONENT ;
--------------------------------------------------------
begin
dav<="1";
U1: div25mhz PORT MAP (CLK,cable1);
U2: divkhz PORT MAP (cable1,cable2);
u3: lcd_drv PORT MAP (CABLE1,CABLE5,CABLE2,CABLE3,DAV,CABLE4,DOUT,LCD_SEL,LCD_RW,LCD_EN);
U4: holamundo PORT MAP(CABLE4,CLK,CABLE5,CABLE3);
end Behavioral;
------------------------------------------------------------------
--------------------------------------------------------------------
----------------------------------------------------------------------
Gracias !!!!
