Hola que tal...
Saludos a todos los miembros y visitantes de la comunidad.
Soy nuevo en esto de la programacion de los FPGA's y me he topado con un gran problema.
He estado trabajando con el kid de evaluacion spartan 3E Starter ( XCS500E ).
Esta dispone de un ADC el cual necesito programar. Ya he intentado programarlo
muchas veces, pero no logro hacer que funcione.
Lo que me parece curioso es que ya he leido hacerca de como hacer la programacion,
sigo los consejos al pie de la letra y nada..
Aqui les dejo un programa que me hicieron favor de pasarme.
( este no tiene errores salvo algunos comentarios )
Me gustaria que alguien pudiera programarlo en su targeta y viera si funciona,
esto para descartar que mi targeta no este quemada
...
Muchas gracias.
nota: utilice los puertos J1 y J2 de la spartan-3E para poder ver totalmente la salida de la conversion del canal 0
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity COPIA is
Port (
clock : in STD_LOGIC; -- global clock
rst : in STD_LOGIC; -- global rst
-- user signal
ce_amp : in STD_LOGIC := '0'; -- Botón para iniciar la prog. del amp
goconv : in STD_LOGIC := '0';-- inicia la conversion del ADC
ready : out STD_LOGIC := '0'; --led que avisa que al amp esta programado
-- ADC in/out signal
SPI_MISO : in std_logic; --adc status report unused
ACONV : out STD_LOGIC :='0'; -- start conversion
--ADC0 : out std_logic_vector(13 downto 0) := (others => '0');
ADC1 : out std_logic_vector(13 downto 0) := (others => '0');
-- AMP in/out signal
AMP_CS : out STD_LOGIC; -- AMP chip select
MOSI : out STD_LOGIC; -- data to programmable amplifier
SCK : out STD_LOGIC
);
end COPIA;
architecture Behavioral of COPIA is
constant gain : std_logic_vector(7 downto 0) := "00010001; --ganancia de -1
type state_type is (IDLE, START,START2,HI,HI_DUMMY,LO,LO_DUMMY,FINE,IDLE_AD, START_AD,HI_AD,LO_AD,FINE_AD);
signal next_state, state : state_type;
signal counter : integer range 0 to 35 :=0;
signal amp_bit_count : integer range 0 to 15 := 0;
begin
process(ce_amp,goconv,state,counter,amp_bit_count) is
begin
case state is
when IDLE =>
if ce_amp = '1' then ---espera hasta poner en 1 el boton
next_state <= START;
else
next_state <= IDLE;
end if;
when START =>
next_state <= START2;
when START2 =>
next_state <= HI;
when HI =>
if counter = 2 then
next_state <= HI_DUMMY;
else
next_state <= HI;
end if;
when HI_DUMMY =>
next_state <= LO;
when LO =>
if counter = 2 then
next_state <= LO_DUMMY;
else
next_state <= LO;
end if;
when LO_DUMMY =>
if amp_bit_count=8 then
next_state <= FINE;
else
next_state <= HI;
end if;
when FINE =>
next_state <= IDLE_AD;--start to sample
------INICIA ADC-------------
when IDLE_AD =>
if goconv ='1' then
next_state <= START_AD;
else
next_state <= IDLE_AD;
end if;
when START_AD =>
next_state <= HI_AD;
when HI_AD =>
next_state <= LO_AD;
when LO_AD =>
if counter = 34 then
next_state <= FINE_AD;
else
next_state <= HI_AD;
end if;
when FINE_AD =>
next_state <= IDLE_AD;--inicia una nueva conversion.
when others =>
next_state <= IDLE_AD;
end case;
end process;
------------------------------------------------------------------------------
process (clock,rst) is
variable index1 : integer range 0 to 15;
variable index2 : integer range 0 to 15;
begin
if rst = '1' then
state <= IDLE;
elsif clock'event and clock ='1' then
-- global assign
state <= next_state;
ready <= '0'; -- busy, setup AMP, acquiring by ADC
case state is
when IDLE =>
SCK <= '0';
AMP_CS <= '1';
MOSI <='0';
counter <=0;
ADC1 <= (others => '0');
when START =>
AMP_CS <= '0';
amp_bit_count <= 0;
index1 := 7; -- 8 bit value
when START2 =>
MOSI <= gain(index1); -- first assign, next on LO_DUMMY
when HI =>
SCK <= '1';
counter <= counter +1;
when HI_DUMMY =>
amp_bit_count <= amp_bit_count + 1;
counter <=0;
when LO =>
SCK <= '0';
counter <= counter +1;
if counter = 1 then
if index1 > 0 then
index1 := index1-1;
end if;
end if;
when LO_DUMMY =>
MOSI <= gain(index1);
counter <=0;
when FINE =>
AMP_CS <='1';
SCK <= '0';
MOSI <= '0';
------INICIA ADC----
when IDLE_AD =>
ready <= '1'; -- setup AMP complete, waiting goconv enable
SCK <= '0';
ACONV <= '0';
when START_AD =>
--clean register
--ADC0 <= (others => '0');
ADC1 <= (others => '0');
SCK <= '0';
ACONV <= '1';
counter <= 0;
index1 := 13; -- 14 bit value
index2 := 13; -- 14 bit value
when HI_AD =>
SCK <= '1';
ACONV <= '0';
counter <= counter +1;
when LO_AD =>
SCK <= '0';
ACONV <= '0';
if(counter>2 and counter<17) then
-- rappresentazione in complemento a 2
if index1 = 13 then
--ADC0(index1) <= not SPI_MISO;
ADC1(index2) <= not SPI_MISO;
else
--ADC0(index1) <= SPI_MISO;
ADC1(index2) <= SPI_MISO;
end if;
if index1 > 0 then
index1 := index1 -1;
end if;
elsif(counter > 18 and counter < 33) then
-- rappresentazione in complemento a 2
if index2 = 13 then
ADC1(index2) <= not SPI_MISO;
--ADC0(index1) <= not SPI_MISO;
else
ADC1(index2) <= SPI_MISO;
--ADC0(index1) <= SPI_MISO;
end if;
if index2 > 0 then -- fatal error on modelsim
index2 := index2 -1;
end if;
else
end if;
when FINE_AD =>
counter <= 0;
SCK <= '0';
ACONV <= '0';
when others =>
SCK <= '0';
ACONV <= '0';
AMP_CS <= '1';
MOSI <='0';
amp_bit_count <= 0;
end case;
end if;
end process;
end Behavioral;
------------------UCF-------------------------------
NET "ACONV" LOC = "P11" ;
NET "ADC1<0>" LOC = "B6" ;
NET "ADC1<10>" LOC = "C11" ;
NET "ADC1<11>" LOC = "D11" ;
NET "ADC1<12>" LOC = "E9" ;
NET "ADC1<13>" LOC = "F9" ;
NET "ADC1<1>" LOC = "A6" ;
NET "ADC1<2>" LOC = "C5" ;
NET "ADC1<3>" LOC = "D5" ;
NET "ADC1<4>" LOC = "A4" ;
NET "ADC1<5>" LOC = "B4" ;
NET "ADC1<6>" LOC = "F12" ;
NET "ADC1<7>" LOC = "E12" ;
NET "ADC1<8>" LOC = "E11" ;
NET "ADC1<9>" LOC = "F11" ;
NET "AMP_CS" LOC = "N7" ;
NET "ce_amp" LOC = "L13" ;
NET "clock" LOC = "C9" ;
NET "goconv" LOC = "L14" ;
NET "MOSI" LOC = "T4" ;
NET "ready" LOC = "F7" ;
NET "rst" LOC = "N17" ;
NET "SCK" LOC = "U16" ;
NET "SPI_MISO" LOC = "N10" ;
