Hola
Tengo un 16F877A y estoy haciendo pruebas infructuosas para convertir un voltaje que entra por AN0, el voltaje está en un rango 4,20~5,00 v.
Cuando energizo el PIC, los 10 bits de ADRH y ADRL ( los 8+2 en 1) quedan en alto aunque cambie el voltaje de AN0. Escribí el procedimiento de adquisición como indica el datasheet, y estoy en un punto muerto, no se por donde continuar.
El proceso que realizo es el siguiente:
;##############################################################################
; CABECERA ****
;**************
list p=P16F877A ; list directive to define processor
#include <P16F877A.INC> ; processor specific variable definitions
;------------------------------------------------------------------------------
__CONFIG _XT_OSC & _DEBUG_OFF & _WDT_OFF & _PWRTE_OFF & _BODEN_OFF & _LVP_OFF & _CPD_OFF & _CP_OFF & _DEBUG_OFF
;##############################################################################
; VARIABLES ****
;***************
;-------------------------------------------
; 0x20 ~ 0x7F - Banco 0 | RP1 : 0 RP0 : 0
;-------------------------------------------
w_temp equ 0x20 ; variable used for context saving
status_temp equ 0x21 ; variable used for context saving
pclath_temp equ 0x22 ; variable used for context saving
ADbyte_bajo equ 0x23
ADbyte_alto equ 0x24
; variables de los temporizadores
Tmp25usDly0 equ 0x25
Tmp25usDly1 equ 0x26
PDel0 equ 0x27
PDel1 equ 0x28
T500mSegDly0 org 0x29
T500mSegDly1 org 0x2A
;##############################################################################
; DIRECCIONES ****
;*****************
ORG 0x000 ; processor reset vector
goto Inicio ; go to beginning of program
ORG 0x004 ; interrupt vector location
goto SDI
org 0x005
;##############################################################################
; INTERRUPCIONES ****
;********************
SDI movwf w_temp ; Copy W to TEMP register
swapf STATUS, w ; Swap status to be saved into W
clrf STATUS ; bank 0, regardless of current bank, Clears IRP,RP1,RP0
movwf status_temp ; Save status to bank zero STATUS_TEMP register
movf PCLATH, w ; Only required if using pages 1, 2 and/or 3
movwf pclath_temp ; Save PCLATH into W
clrf PCLATH ; Page zero, regardless of current page
;----------------------------------------------------------------------
;
btfss PIR1, ADIF
goto SDI_Fin_AD
movlw ADRESH
movwf ADbyte_alto
movlw ADRESL
movwf ADbyte_bajo
call EscrBatLed
bcf PIR1, ADIF
bcf ADCON0, ADON ; apaga el módolo A/D
SDI_Fin_AD
;
;----------------------------------------------------------------------
movf pclath_temp, w ; Restore PCLATH
movwf PCLATH ; Move W into PCLATH
swapf status_temp, w ; Swap STATUS_TEMP register into W;(sets bank to original state)
movwf STATUS ; Move W into STATUS register
swapf w_temp, f ; Swap W_TEMP
swapf w_temp, w ; Swap W_TEMP into W
; borra la bandera de la interrupción
retfie
;##############################################################################
; Batería ****
;*************
TestBateria ; Configure analog pins/voltage reference and digital I/O
bcf STATUS, RP1 ; cambia al -----------------------
bsf STATUS, RP0 ; **** BANCO 1 |
bsf ADCON1, PCFG3 ; AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
bsf ADCON1, PCFG2 ; D D D D D D D A
bsf ADCON1, PCFG1 ; PCFG3 PCFG2 PCFG1 PCFG0
bcf ADCON1, PCFG0 ; 1 1 1 0
bcf ADCON1, ADFM ; Left justified. Six (6) Least Significant bits of ADRESL are read as ‘0’.
bcf STATUS, RP1 ; vuelve al -----------------------
bcf STATUS, RP0 ; **** BANCO 0 |
; Select A/D input channel
bcf ADCON0, CHS2 ; 000 = Channel 0 (AN0)
bcf ADCON0, CHS1
bcf ADCON0, CHS0
; Select A/D conversion clock
bcf STATUS, RP1 ; cambia al -----------------------
bsf STATUS, RP0 ; **** BANCO 1 |
bcf ADCON1, ADCS2 ; A/D Conversion Clock Select bit
bcf STATUS, RP1 ; vuelve al -----------------------
bcf STATUS, RP0 ; **** BANCO 0 |
bsf ADCON0, ADCS1 ; FOSC/32 Maximum Device Frequency 20 Mhz
bcf ADCON0, ADCS0
; Turn on A/D module
bsf ADCON0, ADON
; Wait the required acquisition time
call Tmp500mSeg
; Start conversion
bsf ADCON0, GO_DONE
; Configure A/D interrupt
bcf PIR1, ADIF
bsf PIE1, ADIE
bsf INTCON, PEIE
bsf INTCON, GIE
return ; queda a la espera de la int de fin de conversión
;------------------------------------------------------------------------------
EscrBatLed ;-------------------------
clrf PORTC
clrf PORTD
;-------------------------
btfss ADbyte_alto, 0
bcf PORTD, 2
bsf PORTD, 2
btfss ADbyte_alto, 1
bcf PORTD, 3
bsf PORTD, 3
btfss ADbyte_alto, 2
bcf PORTC, 4
bsf PORTC, 4
btfss ADbyte_alto, 3
bcf PORTC, 5
bsf PORTC, 5
btfss ADbyte_alto, 4
bcf PORTC, 6
bsf PORTC, 6
btfss ADbyte_alto, 5
bcf PORTC, 7
bsf PORTC, 7
btfss ADbyte_alto, 6
bcf PORTD, 4
bsf PORTD, 4
btfss ADbyte_alto, 7
bcf PORTD, 5
bsf PORTD, 5
btfss ADbyte_bajo, 0
bcf PORTD, 6
bsf PORTD, 6
btfss ADbyte_bajo, 1
bcf PORTD, 7
bsf PORTD, 7
return
;##############################################################################
; INICIO ****
;************
Inicio clrf PCLATH ; ensure page bits are cleared
; seteos en el banco 0 ------------------------------------------------
bcf STATUS, RP1 ; cambia al
bcf STATUS, RP0 ; banco 0
bcf T1CON, TMR1CS ; Internal clock (FOSC/4)
bcf T1CON, TMR1ON ; Stops Timer1
bcf T2CON, TMR2ON ; Timer2 is off
movlw 0x00
movwf CCP1CON ; Capture/Compare/PWM disabled (resets CCP1 module)
movlw 0x00
movwf CCP2CON ; Capture/Compare/PWM disabled (resets CCP2 module)
bcf SSPCON, SSPEN ; Disables the serial port and configures these pins as I/O port pins
bcf RCSTA, SPEN ; Serial port disabled
; seteos en el banco 1 ------------------------------------------------
bcf STATUS, RP1 ; cambia al
bsf STATUS, RP0 ; banco 1
; otros seteos ----------------------
bcf OPTION_REG, NOT_RBPU ; PORTB pull-ups are disabled
bcf OPTION_REG, INTEDG ; Interrupt on falling edge of RB0/INT pin
bcf OPTION_REG, T0CS ; Internal instruction cycle clock (CLKO)
bsf OPTION_REG, T0SE ; Increment TMR0 on high-to-low transition on RA4/T0CKI pin
bcf OPTION_REG, PSA ; Prescaler is assigned to the Timer0 module
bcf INTCON, GIE ; Disables all unmasked interrupts ####
bcf INTCON, PEIE ; Disables all peripheral interrupts ####
bcf INTCON, TMR0IE ; Disables the TMR0 interrupt
bcf INTCON, INTE ; Disables the RB0/INT external interrupt ####
bcf INTCON, RBIE ; Disables the RB port change interrupt ####
bcf PIE1, PSPIE ; Disables the PSP read/write interrupt
bsf PIE1, ADIE ; Enables the A/D converter interrupt ####
bcf PIE1, RCIE ; Disables the USART receive interrupt
bcf PIE1, TXIE ; Disables the USART transmit interrupt
bcf PIE1, SSPIE ; Disables the SSP interrupt
bcf PIE1, CCP1IE ; Disables the CCP1 interrupt
bcf PIE1, TMR2IE ; Disables the TMR2 to PR2 match interrupt
bcf PIE1, TMR1IE ; Disables the TMR1 overflow interrupt
bcf PIE2, CMIE ; Disable the comparator interrupt
bcf PIE2, EEIE ; Disable EEPROM write interrupt
bcf PIE2, BCLIE ; Disable bus collision interrupt
bcf PIE2, CCP2IE ; Disables the CCP2 interrupt
bcf TRISE, PSPMODE ; PORTD functions in general purpose I/O mode
movlw 0x07
movwf CMCON ; Comparators Off
; configuración de puertos ----------
movlw 0x01
movwf TRISA
movlw 0x00
movwf TRISC
movlw 0x00
movwf TRISD
; seteos en el banco 2 --------------------------------------------
bsf STATUS, RP1 ; cambia al
bcf STATUS, RP0 ; banco 2
; seteos en el banco 3 --------------------------------------------
bsf STATUS, RP1 ; cambia al
bsf STATUS, RP0 ; banco 3
bcf STATUS, RP1 ; vuelve al
bcf STATUS, RP0 ; banco 0
;------------------------------------------------------------------
goto Dormir
;##############################################################################
; Dormir ****
;************
Dormir call TestBateria
call Tmp500mSeg
goto Dormir
;##############################################################################
; Temporizadores ****
;********************
Tmp25us movlw .44 ; 1 set number of repetitions (B)
movwf Tmp25usDly0 ; 1 |
Tmp25usLp1 movlw .141 ; 1 set number of repetitions (A)
movwf Tmp25usDly1 ; 1 |
Tmp25usLp2 clrwdt ; 1 clear watchdog
decfsz Tmp25usDly1, 1 ; 1 + (1) is the time over? (A)
goto Tmp25usLp2 ; 2 no, loop
decfsz Tmp25usDly0, 1 ; 1 + (1) is the time over? (B)
goto Tmp25usLp1 ; 2 no, loop
Tmp25usDLp1 goto Tmp25usDLp2 ; 2 cycles delay
Tmp25usDLp2 clrwdt ; 1 cycle delay
return ; 2+2 Done
;------------------------------------------------------------------------------
;-------------------------------------------------------------
; Code generated by PDEL ver 1.0 on 14/02/2009 at 09:57:58 p.m.
; Description: Waits 250000 cycles
;-------------------------------------------------------------
PDelay movlw .197 ; 1 set number of repetitions (B)
movwf PDel0 ; 1 |
PLoop1 movlw .253 ; 1 set number of repetitions (A)
movwf PDel1 ; 1 |
PLoop2 clrwdt ; 1 clear watchdog
clrwdt ; 1 cycle delay
decfsz PDel1, 1 ; 1 + (1) is the time over? (A)
goto PLoop2 ; 2 no, loop
decfsz PDel0, 1 ; 1 + (1) is the time over? (B)
goto PLoop1 ; 2 no, loop
PDelL1 goto PDelL2 ; 2 cycles delay
PDelL2
return ; 2+2 Done
;-------------------------------------------------------------
; Code generated by PDEL ver 1.0 on 23/02/2009 at 04:40:04 p.m.
; Description: Waits 500000 cycles
;-------------------------------------------------------------
Tmp500mSeg movlw .239 ; 1 set number of repetitions (B)
movwf T500mSegDly0 ; 1 |
T500mSegLp1 movlw .232 ; 1 set number of repetitions (A)
movwf T500mSegDly1 ; 1 |
T500mSegLp2 clrwdt ; 1 clear watchdog
T500mSegDlL1 goto T500mSegDlL2 ; 2 cycles delay
T500mSegDlL2 goto T500mSegDlL3 ; 2 cycles delay
T500mSegDlL3 clrwdt ; 1 cycle delay
decfsz T500mSegDly1, 1 ; 1 + (1) is the time over? (A)
goto T500mSegLp2 ; 2 no, loop
decfsz T500mSegDly0, 1 ; 1 + (1) is the time over? (B)
goto T500mSegLp1 ; 2 no, loop
T500mSegDlL4 goto T500mSegDlL5 ; 2 cycles delay
T500mSegDlL5 goto T500mSegDlL6 ; 2 cycles delay
T500mSegDlL6 goto T500mSegDlL7 ; 2 cycles delay
T500mSegDlL7 clrwdt ; 1 cycle delay
return ; 2+2 Done
;-------------------------------------------------------------
;##############################################################################
end
;##############################################################################
Muchísimas gracias por cualquier ayuda o pista.
Saludos.-
