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-- Company:
-- Engineer:
--
-- Create Date: 17:42:58 08/01/2012
-- Design Name:
-- Module Name: DECO_DEC - ESTRUCTURAL
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity inversor is
Port (a: in STD_LOGIC;
not_a: out STD_LOGIC);
end inversor;
architecture f_d_d_inversor of inversor is
begin
not_a<= not a;
end f_d_d_inversor;
--fin inversor
--and2ent
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity nand4ent is
Port (e1: in STD_LOGIC;
e2: in STD_LOGIC;
output: out STD_LOGIC);
end nand4ent;
architecture f_d_d_nand4ent of nand4ent is
begin
output<= not(e1 and e2);
end f_d_d_nand4ent;
--fin and2ent
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DECO_DEC is
Port ( a,b,c,d : in STD_LOGIC;
x1,x2,x3,x4,x5,x6,x7,x8,x9,x10 : out STD_LOGIC);
end DECO_DEC;
architecture ESTRUCTURAL of DECO_DEC is
--Definición de los componentes que forman parte del DECO_DEC
component nand2ent
port(e1,e2:in std_logic;output:out STD_LOGIC);
end component;
component inversor
port(e:in std_logic;not_e:out std_logic);
end component;
signal a,not a,b,not b,c,not c,d, not d,: std_logic; --Señales internas del esquema
begin
U1= nand4ent port map(a,not b, not c,d,x1);
U2= nand4ent port map(not a,not c,not b,d,x2);
U3= nand4ent port map(a,b,c,not d,x3);
U4= nand4ent port map(not a,b,c,not d,x4);
U5= nand4ent port map(a,not b,c,not d,x5);
U6= nand4ent port map(not a,not b,c,not d,x6);
U7= nand4ent port map(a,b,not c,not d,x7);
U8= nand4ent port map(not a,b,not c,not d,x8);
U9= nand4ent port map(a,not b,not c,not d,x9);
U10= nand4ent port map(not a,not b,not c,not d);
U11= inversor port map(not d,d);
U12= inversor port map(d,not d);
U13= inversor port map(not c,c);
U14= inversor port map(c,not c);
U15= inversor port map(not b,b);
U16= inversor port map(b,not b);
U17= inversor port map(not a,a);
U18= inversor port map(a,not a);
end ESTRUCTURAL;
