El grader del Lab10 me tiene loco, no consigo pasar de 65 puntos. He mirado en el foro de piazza pero no consigo ver la solución. ¿Alguien sabe como se soluciona?
// ***** 0. Documentation Section *****
// TableTrafficLight.c for Lab 10
// Runs on LM4F120/TM4C123
// Index implementation of a Moore finite state machine to operate a traffic light.
// Daniel Valvano, Jonathan Valvano
// November 7, 2013
// east/west red light connected to PB5
// east/west yellow light connected to PB4
// east/west green light connected to PB3
// north/south facing red light connected to PB2
// north/south facing yellow light connected to PB1
// north/south facing green light connected to PB0
// pedestrian detector connected to PE2 (1=pedestrian present)
// north/south car detector connected to PE1 (1=car present)
// east/west car detector connected to PE0 (1=car present)
// "walk" light connected to PF3 (built-in green LED)
// "don't walk" light connected to PF1 (built-in red LED)
// ***** 1. Pre-processor Directives Section *****
#include "TExaS.h"
#include "tm4c123gh6pm.h"
// ***** 2. Global Declarations Section *****
// FUNCTION PROTOTYPES: Each subroutine defined
void DisableInterrupts(void); // Disable interrupts
void EnableInterrupts(void); // Enable interrupts
void PortF_Init(void); // Inicializar las luces de los peatones PF3 PF1
void PortB_Init(void); // Inicializar las luces de los semaforos PB[5-0]
void PortE_Init(void); // Inicializar los sensores PE[2-0]
// Initialize SysTick with busy wait running at bus clock.
void SysTick_Init(void);
// Time delay using busy wait.
// The delay parameter is in units of the core clock. (units of 12.5 nsec for 80 MHz clock)
void SysTick_Wait(unsigned long delay);
// Time delay using busy wait.
// This assumes 80 MHz system clock.
void SysTick_Wait10ms(unsigned long delay);
// ***** 3. Subroutines Section *****
// Linked data structure
struct State {
unsigned long Out;
unsigned long OutPedest;
unsigned long Time;
unsigned long Next[8];};
typedef const struct State STyp;
#define WaitAll 0
#define GoWest 1
#define GoWestWait 2
#define GoSouth 3
#define DoSouthWait 4
#define GoPedest 5
#define HurryUp1 6
#define HurryUp2 7
#define HurryUp3 8
#define HurryUp4 9
#define GoWestSouth 10
#define GoSouthWest 11
#define GoWestSouthPedest 12
STyp FSM[15] = {
{0x24,0x02,50,{0,1,3,2,5,1,3,1}},
{0x0c,0x02,100,{2,1,2,2,2,2,2,2}},
{0x14,0x02,50,{0,0,0,10,5,5,3,3}},
{0x21,0x02,100,{4,4,3,4,4,4,4,4}},
{0x22,0x02,50,{0,0,0,11,5,5,5,12}},
{0x24,0x08,100,{6,6,6,6,5,6,6,6}},
{0x24,0x02,50,{7,7,7,7,7,7,7,7}},
{0x24,0x08,50,{8,8,8,8,8,8,8,8}},
{0x24,0x02,50,{9,9,9,9,9,9,9,9}},
{0x24,0x08,50,{13,13,13,13,13,13,13,13}},
{0x24,0x02,25,{0,1,3,3,5,5,3,3}},
{0x24,0x02,25,{0,1,3,1,5,5,1,5}},
{0x24,0x02,25,{0,1,3,1,5,5,5,5}},
{0x24,0x02,50,{14,14,14,14,14,14,14,14}},
{0x24,0x08,50,{0,0,0,0,0,0,0,0}}
};
unsigned char cState; // current State (0 to 14)
unsigned char input;
int main(void){
TExaS_Init(SW_PIN_PE210, LED_PIN_PB543210); // activate grader and set system clock to 80 MHz
PortF_Init();
PortE_Init();
PortB_Init();
SysTick_Init();
cState = 0;
EnableInterrupts();
while(1){
GPIO_PORTB_DATA_R = FSM[cState].Out;
GPIO_PORTF_DATA_R = FSM[cState].OutPedest;
SysTick_Wait10ms(FSM[cState].Time);
input = GPIO_PORTE_DATA_R&0x07; // Enmascaramos el resto de entradas que no sean PE[2-0]
cState = FSM[cState].Next[input];
}
}
void PortF_Init(void){ volatile unsigned long delay;
SYSCTL_RCGC2_R |= 0x00000020; // 1) activate clock for Port F
delay = SYSCTL_RCGC2_R; // allow time for clock to start
GPIO_PORTF_AMSEL_R = 0x00; // 2) disable analog on PF
GPIO_PORTF_PCTL_R = 0x00000000; // 3) PCTL GPIO on PF4-0
GPIO_PORTF_DIR_R |= 0x0A; // 4) PB[0-5] is out
GPIO_PORTF_AFSEL_R &= ~0x0A; // 5) disable alt funct on PF7-0
GPIO_PORTF_PUR_R |= 0x0A; // enable pull-up on PF4
GPIO_PORTF_DEN_R |= 0x0A; // 6) enable digital I/O on PF4
}
void PortE_Init(void){ volatile unsigned long delay;
SYSCTL_RCGC2_R |= 0x00000010; // 1) activate clock for Port F
delay = SYSCTL_RCGC2_R; // allow time for clock to start
GPIO_PORTE_AMSEL_R = 0x00; // 2) disable analog on PE
GPIO_PORTE_PCTL_R = 0x00000000; // 3) PCTL GPIO on PE2-0
GPIO_PORTE_DIR_R &= ~0x07; // 4) PE[2-0] in
GPIO_PORTE_AFSEL_R &= ~0x07; // 5) disable alt funct on PE7-0
GPIO_PORTE_PUR_R |= 0x07; // enable pull-up on PE[2-0]
GPIO_PORTE_DEN_R |= 0x07; // 6) enable digital I/O on PE[2-0]
}
void PortB_Init(void){ volatile unsigned long delay;
SYSCTL_RCGC2_R |= 0x00000002; // 1) activate clock for Port B
delay = SYSCTL_RCGC2_R; // allow time for clock to start
GPIO_PORTB_AMSEL_R = 0x00; // 3) disable analog on PB
GPIO_PORTB_PCTL_R = 0x00000000; // 4) PCTL GPIO on PB0
GPIO_PORTB_DIR_R |= 0x3F; // 5) PB[0-5] is out
GPIO_PORTB_AFSEL_R &= ~0x3F; // 6) disable alt funct on PB0
GPIO_PORTB_DEN_R |= 0x3F; // 7) enable digital I/O on PB0
}
void SysTick_Init(void){
NVIC_ST_CTRL_R = 0; // disable SysTick during setup
NVIC_ST_CTRL_R = 0x00000005; // enable SysTick with core clock
}
// The delay parameter is in units of the 80 MHz core clock. (12.5 ns)
void SysTick_Wait(unsigned long delay){
NVIC_ST_RELOAD_R = delay-1; // number of counts to wait
NVIC_ST_CURRENT_R = 0; // any value written to CURRENT clears
while((NVIC_ST_CTRL_R&0x00010000)==0){ // wait for count flag
}
}
// 10000us equals 10ms
void SysTick_Wait10ms(unsigned long delay){
unsigned long i;
for(i=0; i<delay; i++){
SysTick_Wait(800000); // wait 10ms
}
}
Y esta es la salida
Running with Code Size Limit: 32K
Load "C:\\Keil4\\Labware\\Lab10_TrafficLight\\Lab10.axf"
*** Restricted Version with 32768 Byte Code Size Limit
*** Currently used: 19052 Bytes (58%)
Start grading
Clock rate appears to be : 80 MHz
Running 5 tests
0) Initialization tests :
- (PE2-0) have been selected as the input pins
- Verifying input configuration...
Pass: PORTE DEN bits (2-0) are high
Pass: PORTE DIR bits (2-0) are low
Pass: PORTE AFSEL bits (2-0) are low
Pass: PORTE AMSEL bits (2-0) are low
Pass: PORTE PCTL bits (11-0) are low
- (PB5-0) have been selected as the output pins
- Verifying output configuration...
Pass: PORTB DEN bits (5-0) are high
Pass: PORTB DIR bits (5-0) are high
Pass: PORTB AFSEL bits (5-0) are low
Pass: PORTB AMSEL bits (5-0) are low
Pass: PORTB PCTL bits (23-0) are low
1) Servicing all 3 requests, lights should make a complete cycle
FSM: Transition: 1 to 2
FSM: Transition: 2 to 3
FSM: Transition: 3 to 4
FSM: Transition: 4 to 5
FSM: Transition: 5 to 1
FSM: Transition: 1 to 6
FSM: Transition: 6 to 1
FSM: Transition: 1 to 6
FSM: Transition: 6 to 1
FSM: Transition: 1 to 6
FSM: Transition: 6 to 1
FSM: Transition: 1 to 2
FSM: Transition: 2 to 3
FSM: Transition: 3 to 4
FSM: Transition: 4 to 5
FSM: Transition: 5 to 1
FSM: Transition: 1 to 6
FSM: Transition: 6 to 1
FSM: Transition: 1 to 6
FSM: Transition: 6 to 1
FSM: Transition: 1 to 6
FSM: Transition: 6 to 1
FSM: Transition: 1 to 2
FSM: Transition: 2 to 3
FSM: Transition: 3 to 4
FSM: Transition: 4 to 5
FSM: Transition: 5 to 1
FSM: Transition: 1 to 6
* FAIL: Did not service all requests before the timeout
Pass: South request was serviced
Pass: West request was serviced
* FAIL: Walk request was not serviced
- Test FAILED
2) Servicing walk button, walk light should come on
Pass: All requests were serviced
Pass: Walk request was serviced
- Test PASSED
3) Servicing west button, west green light should come on
FSM: Transition: 6 to 1
FSM: Transition: 1 to 6
FSM: Transition: 6 to 1
FSM: Transition: 1 to 6
FSM: Transition: 6 to 1
FSM: Transition: 1 to 2
Pass: All requests were serviced
Pass: West request was serviced
- Test PASSED
4) Servicing south button, south green light should come on
FSM: Transition: 2 to 3
FSM: Transition: 3 to 1
FSM: Transition: 1 to 4
Pass: All requests were serviced
Pass: South request was serviced
- Test PASSED
Done grading. Score is 65
Muchas gracias.
Un saludo.
