Amigos, tengo un problema muy pero muy raro, tengo el siguiente código el cual pongo abajo y resulta que cuando debe de hacer que el led encienda y apague no lo hace, se queda encendido, pero cuando le hago debug, si funciona solo que salta hacia adelante y atrás varias veces pero si funciona repito
/*
* File: mainpruebas2.c
* Author: l
*
* Created on July 7, 2015, 1:32 PM
*/
// #pragma config statements should precede project file includes.
// Use project enums instead of #define for ON and OFF.
// CONFIG1H
#pragma config OSC = HS // Oscillator Selection bits (HS oscillator)
#pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
#pragma config IESO = OFF // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)
// CONFIG2L
#pragma config PWRT = ON // Power-up Timer Enable bit (PWRT enabled)
#pragma config BOREN = SBORDIS // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled))
#pragma config BORV = 3 // Brown Out Reset Voltage bits (Minimum setting)
// CONFIG2H
#pragma config WDT = ON // Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))
#pragma config WDTPS = 32768 // Watchdog Timer Postscale Select bits (1:32768)
// CONFIG3H
#pragma config CCP2MX = PORTC // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
#pragma config PBADEN = OFF // PORTB A/D Enable bit (PORTB<4:0> pins are configured as analog input channels on Reset)
#pragma config LPT1OSC = OFF // Low-Power Timer1 Oscillator Enable bit (Timer1 configured for higher power operation)
#pragma config MCLRE = OFF // MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled)
// CONFIG4L
#pragma config STVREN = ON // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
#pragma config LVP = ON // Single-Supply ICSP Enable bit (Single-Supply ICSP enabled)
#pragma config XINST = OFF // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))
// CONFIG5L
#pragma config CP0 = OFF // Code Protection bit (Block 0 (000800-003FFFh) not code-protected)
#pragma config CP1 = OFF // Code Protection bit (Block 1 (004000-007FFFh) not code-protected)
#pragma config CP2 = OFF // Code Protection bit (Block 2 (008000-00BFFFh) not code-protected)
#pragma config CP3 = OFF // Code Protection bit (Block 3 (00C000-00FFFFh) not code-protected)
// CONFIG5H
#pragma config CPB = OFF // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected)
#pragma config CPD = OFF // Data EEPROM Code Protection bit (Data EEPROM not code-protected)
// CONFIG6L
#pragma config WRT0 = OFF // Write Protection bit (Block 0 (000800-003FFFh) not write-protected)
#pragma config WRT1 = OFF // Write Protection bit (Block 1 (004000-007FFFh) not write-protected)
#pragma config WRT2 = OFF // Write Protection bit (Block 2 (008000-00BFFFh) not write-protected)
#pragma config WRT3 = OFF // Write Protection bit (Block 3 (00C000-00FFFFh) not write-protected)
// CONFIG6H
#pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
#pragma config WRTB = OFF // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected)
#pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM not write-protected)
// CONFIG7L
#pragma config EBTR0 = OFF // Table Read Protection bit (Block 0 (000800-003FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR1 = OFF // Table Read Protection bit (Block 1 (004000-007FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR2 = OFF // Table Read Protection bit (Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks)
#pragma config EBTR3 = OFF // Table Read Protection bit (Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks)
// CONFIG7H
#pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks)
#include <xc.h>
#include <pic18f4620.h>
#include <delays.h>
#include <stdio.h>
#include <stdlib.h>
#include <plib/usart.h> //Libreria para el manejo del modulo USART
#define _XTAL_FREQ 20000000
//#define __delay_ms(x) _delay((unsigned long)((x)*(_XTAL_FREQ/20000000.0)))
int i, pin, puerto;
int k = 0;
char CaracterRx;
char MensajeTx[8];
void tiempo()
{
for(i=0;i<20;i++) { __delay_ms(25); }
}
void main ()
{
TRISB = 0b00000000; // Configuro puerto B como salidas
OpenUSART(USART_TX_INT_OFF &
USART_RX_INT_ON & //Activar la interrupcion por la recepcion de dato del buffer de Rx del USART
USART_ASYNCH_MODE & //Modo asincrono (fullduplex)
USART_EIGHT_BIT & //8 bits de datos
USART_CONT_RX & //Recepción continua
USART_BRGH_HIGH, 129); //9600 Baudios
INTCONbits.PEIE = 1; //Activamos interrupcion de perifericos
INTCONbits.GIE = 1; //Activamos las interrupciones globales
LATB=0x00;
while (1) // Bucle infinito
{
pin=MensajeTx[1];
if(MensajeTx[2]=='6')
{
puerto=0x8A;
}
CLRWDT();
switch(MensajeTx[0])
{
case '&': //Caracter general
if(MensajeTx[3]=='f')
{
if(MensajeTx[4]=='o')
{
FSR0L=puerto;
FSR0H=0x0F;
INDF0=INDF0 | pin;
} else
{
pin=pin^0xFF;
FSR0L=puerto;
FSR0H=0x0F;
INDF0=INDF0 & pin;
}
}
else
{
LATB=0x10;
tiempo();
LATB=0x00;
}
break; //Fin caracter general
}
}
}
void interrupt Interrupcion() //Funcion que atiende las interrupciones
{
getsUSART((char *)MensajeTx,7);
PIR1bits.RCIF = 0; //Desactivamos la bandera de recepción en el buffer de entrada del USART
}
