Hola, tengo un multiplicador de pezaris hecho para 5 bits. No me da ningun error al compilar, pero cuando ejecuto la simulacion, el resultado sale indefinido, pero no se como corregirlo. ¿Que puedo hacer para que funcione perfectamente? Os agradecería muchísimo vuestra ayuda. Aqui os dejo el código:
-- Entidad del multiplicador de pezaris
library IEEE;
use IEEE.std_logic_1164.all;
package tipos is
type tablaBits is array (0 to 5,8 downto 0) of std_logic;
end tipos;
library IEEE;
use IEEE.std_logic_1164.all;
use work.tipos.all;
entity multiplicador is
port(factor1,factor2: in std_logic_vector(4 downto 0);
producto: out std_logic_vector(9 downto 0));
end multiplicador;
-- Arquitectura del multiplicador de pezaris
architecture pezaris3 of multiplicador is
signal X:std_logic;
signal Y:std_logic;
signal Z:std_logic;
signal C:tablaBits;
signal S:tablaBits;
begin
mult: process(factor1,factor2)
begin
producto(0) <= factor1(0) and factor2(0);
for i in 0 to 5 loop -- parte positiva y negativa
if (i<4) then -- parte positiva
for j in (i+1) to (i+3) loop
if (i = 0) then -- calcular x
X <= factor1(j) and factor2(0);
elsif (j=i+3) then
X<= factor1(3) and factor2(i);
else
X<= S(i-1,j);
end if;
if (i=0) then -- calcular y
Y <= factor1(j-1) and factor2(1);
else
Y<= C(i-1,j-1);
end if;
if (i=0) or ((j=i+1) and (i=3)) then --calcular z
Z<="0";
elsif (j=i+3 or j=i+2) and (i=3) then
Z <= C(i,j-1);
else
Z<=factor1(j-i-1) and factor2(i+1);
end if;
C(i,j)<=(X and Y) or (Y and Z) or (Z and X);
S(i,j)<=(((not X) and (not Y))and Z) or (((not X) and Y)and (not Z)) or ((X and (not Y))and (not Z)) or ((X and Y)and Z);
end loop;
else -- parte negativa
for j in i to (i+3) loop
if (i=4) and not (j=7) then -- calcular x
X<= S(i-1,j);
elsif (i=4) then
X <= C(i-1,j-1);
elsif (i=5) and (j =
then
X<= factor1(4) and factor2(4);
else
X<= S(i-1,j);
end if;
if (i=4) then -- calcular y
Y<= factor1(i) and factor2(j-i);
else
Y<=C(i-1,j-1);
end if;
if (i=4) then -- calcular z
Z<= factor1(j-i) and factor2(i);
elsif (i=5) and (j=5) then
Z<= "0";
else
Z<= C(i,j-1);
end if;
C(i,j)<= (Z and Y) or ((not X) and Z) or (Y and (not X));
S(i,j)<= (((not X) and (not Y))and Z) or (((not X) and Y)and (not Z)) or ((X and (not Y))and (not Z)) or ((X and Y)and Z);
end loop;
end if;
if (i<3) and (i>0) then -- calcular el producto
producto(i)<= S(i-1,i);
elsif (i=4) then
producto(i)<= S(i,i);
elsif (i=9) then
producto(i)<= C(5,i-1);
elsif (i>0) then
producto(i)<= S(5,i);
end if;
end loop;
end process mult;
end pezaris3;
-- Banco de pruebas del multiplicador de pezaris
library IEEE;
use IEEE.std_logic_1164.all;
use work.tipos.all;
entity bancoPezaris5bits is
end bancoPezaris5bits;
architecture TestBanco of bancoPezaris5bits is
component multiplicador
port(factor1,factor2: in std_logic_vector(4 downto 0);
producto: out std_logic_vector(9 downto 0));
end component;
signal factor1: std_logic_vector (4 downto 0);
signal factor2: std_logic_vector (4 downto 0);
signal producto: std_logic_vector(9 downto 0);
begin
componentePezaris: multiplicador port map (factor1,factor2,producto);
cal:process
begin
factor1 <= "00010";-- 02
factor2 <= "00111" ;
wait for 30 ns;
factor1<= "01111";
factor2 <= "00011";
wait for 30 ns; --03
factor1<="11001";
factor2 <="11101";
wait for 30 ns;
end process cal;
end TestBanco;
